summaryrefslogtreecommitdiff
path: root/drivers/pci
AgeCommit message (Collapse)Author
2018-01-27pci: rmobile: Add RCar Gen2 PCIe controller driverMarek Vasut
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs. The PCIe on Gen2 is used both to connect external PCIe peripherals as well as access the on-SoC USB EHCI controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-01-12drivers: pci: imx: fix enumeration logic errorKoen Vandeputte
By default, the subordinate is set equally to the secondary bus (1) when the RC boots, and does not alter afterwards. This means that theoretically, the highest bus reachable downstream is bus 1. Force the PCIe RC subordinate to 0xff, otherwise no downstream devices will be detected behind bus 1 if the booting OS does not allow enumerating a higher busnr than the subordinate value of the primary bus. Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
2018-01-12pci: imx: request gpio before usePeng Fan
Before use GPIO, we need to request gpio first. Free gpio after use. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-10PCI: Drop CONFIG_TSI108_PCITuomas Tynkkynen
Last user of this option went away in 2015 in commit: d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support") Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2017-11-28Update Paul Burton's email addressPaul Burton
MIPS is no longer a part of Imagination Technologies, and as such my @imgtec.com email address will soon cease to function. This patch updates occurrances of it with my new @mips.com email address, and adds an entry in .mailmap such that git (& tools such as get_maintainer.pl when examining history) will use the new address. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
2017-11-17dm: pci: change bus number register setting compliant with LinuxMinghuan Lian
This patch is to change U-Boot PCI bus assignement compliant with Linux. It means each PCIe controller's bus number is 0, not the current maximum PCI bus number, when start to scan this controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-16pci: mvebu: Increase size of PCIe default mappingVlaoMao
Increase size PCI memory mapping from 32MiB to 128MiB. Signed-off-by: VlaoMao <vlaomao@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-10-12drivers: pci: imx: fix imx_pcie_remove functionSven-Ola Tuecke
We have at least a minor count of boards, that failed to re-initialize PCI express in the Linux kernel. Typical failure rate is 20% on affected boards. This is mitigated by commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function"). However, at least on some i.MX6 custom boards, when calling assert_core_reset() as part of the first-time PCIe init, read access to PCIE_PL_PFLR simply hangs. Surround this readl() with imx_pcie_fix_dabt_handler() does not help. For this reason, the forced LTSSM detection is only used on the second assert_core_reset() that is called shorly before starting the Linux kernel. Signed-off-by: Sven-Ola Tuecke <sven-ola.tuecke@numberfour.eu> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: David Müller <d.mueller@elsoft.ch>
2017-10-06PCI: Add driver for a 'pci-host-ecam-generic' host controllerTuomas Tynkkynen
QEMU emulates such a device with '-machine virt,highmem=off' on ARM. The 'highmem=off' part is required for things to work as the PCI code in U-Boot doesn't seem to support 64-bit BARs. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06pci: layerscape: Use pci_generic_mmap_{read, write}_configTuomas Tynkkynen
Use the new helpers to avoid boilerplate in the driver. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06pci: xilinx: Use pci_generic_mmap_{read, write}_config()Tuomas Tynkkynen
Use the new helper function to avoid boilerplate in the driver. Note that this changes __raw_writel et al. to writel. AFAICT this is no problem because: - The Linux driver for the same hardware uses the non-__raw variants as well (via pci_generic_config_write()). - This driver seems to be used only on MIPS so far, where the __raw and non-__raw accessors are the same. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-06pci: Add helper for implementing memory-mapped config space accessesTuomas Tynkkynen
This sort of pattern for implementing memory-mapped PCI config space accesses appears in U-Boot twice already, and a third user is coming up. So add helper functions to avoid code duplication, similar to how Linux has pci_generic_config_write and pci_generic_config_read. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-22pci: layerscape: Fixup iommu-map for LS208xABharat Bhushan
Commit 0aaa1a9 added support for LS208xA devices but fixing iommu-map property is missing. This patch adds support for fixing iommu-map. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22pci: Remove unnecessary 'default n' from KconfigTuomas Tynkkynen
'default n' is the default anyway so it doesn't need to be specified explicitly, and the rest of the file doesn't specify it either anywhere. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: layerscape: Remove unused field 'hose' from struct ls_pcieTuomas Tynkkynen
This field is no longer used since the DM conversion. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: tegra: Remove unused field 'hose' from struct tegra_pcieTuomas Tynkkynen
This field is no longer used since the DM conversion. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: xilinx: Remove unused field 'hose' from struct xilinx_pcieTuomas Tynkkynen
This field has never been used as the driver has been DM-based since the beginning. Drop it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-22pci: xilinx: Fix doc comments on config space accessorsTuomas Tynkkynen
These take the 'struct udevice *' as an argument, not the 'struct xilinx_pcie *` which is a local variable. Fix the comments to match the code. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-24vbe: Drop vbe_get_video_info()Bin Meng
With DM video, this is not used any more. Drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-08-16env: Rename getenv/_f() to env_get()Simon Glass
We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-09PCI: layerscape: Fix assigning wrong address to LS2088A pcie cfg1 spaceHou Zhiqiang
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add LS2088A series SoC pcie support), which only updated cfg_res.start and did not update the .end field. This causes fdt_resource_size() getting wrong value when calculate the cfg1 space address. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [YS: Revise subject and commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-02Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1046aqds.h include/configs/ls1046ardb.h
2017-08-01soc/fsl-layerscape: Update SVR number for LS2081A and LS2041ASantan Kumar
Update SVR as per the SOC document. -LS2081A: 0x870919 -> 0x870918 -LS2041A: 0x870915 -> 0x870914 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01x86: kconfig: Select PCI and DM_PCIBin Meng
PCI is the de facto interconnect bus in an x86 system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28dm: tegra: pci: Convert to livetreeSimon Glass
Update the tegra pci driver to support a live device tree. Fix the check for nvidia,num-lanes so that an error will actually be detected. Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1 Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-11dm: ofnode: rename ofnode_read_prop() to ofnode_get_property()Masahiro Yamada
This function returns the pointer to the value of a node property. The current name ofnode_read_prop() is confusing. Follow the naming of_get_property() from Linux. The return type (const u32 *) is wrong. DT property values can be strings as well as integers. This is why of_get_property/fdt_getprop returns an opaque pointer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-07-11dm: core: Add functions to obtain node's address/size cellsSimon Glass
The of_n_addr_cells() and of_n_size_cells() functions are useful for getting the size of addresses in a node, but in a few places U-Boot needs to obtain the actual property value for a node without walking up the stack. Add functions for this and just the existing code to use it. Add a comment to the existing ofnode functions which do not do the right thing with a flat tree. This fixes a problem reading PCI addresses. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Beaver, Jetson-TK1
2017-07-03powerpc: remove 4xx supportHeiko Schocher
There was for long time no activity in the 4xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 4xx, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de>
2017-06-27Merge git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/imx6qdl_icore_rqs.h include/configs/imx6ul_geam.h include/configs/imx6ul_isiot.h
2017-06-12powerpc, 8260: remove support for mpc8260Heiko Schocher
There was for long time no activity in the 8260 area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 8260, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01dm: pci: Update uclass to support livetreeSimon Glass
Update the PCI uclass to support livetree. This mostly involves fixing the address decoding from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-31drivers: pci: imx: add imx_pcie_remove functionTim Harvey
There is no dedicated reset signal wired up for the MX6QDL thus if the bootloader enables the link we need some special handling to get the core back into a state where it is safe to touch it for configuration. While there has been some special handling in the Linux kernel to do this, it was removed in 4.11 thus we need to do it properly in the bootloader and therefore without this if you enable PCI in the bootloader you will hang while booting the 4.11 kernel. This puts the PCIe controller back into a safe state for the kernel driver before launching the kernel. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com>
2017-05-26Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-05-23armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-17x86: pci: Allow conditionally run VGA rom in S3Bin Meng
Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can bypass executing VGA roms in S3. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
2017-05-12pci: avoid memory leakxypron.glpk@gmx.de
strdup uses malloc to allocate memory for str. If we cannot bind to the generic driver we should release the memory. The problem was indicated by clang scan-build. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-05-09fix: mvebu: pcie_dw: Allow probing empty PCIe slotsKonstantin Porotchkin
This patch allows probing all PCIe nodes defined in DTS even if there no device connected to such node (no link). Without this fix the driver returns -ENODEV when the PCIe link is down. As result the pci_init function stops scanning bus on first empty PCIe slot and all devices located in higher numbered buses are not discovered. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-04Merge git://git.denx.de/u-boot-dmTom Rini
2017-03-28pcie-layerscape: Fixup iommu-map property of pci nodeBharat Bhushan
This patch fixup iommu-map property on pci node to have a valid mapping of requester-id to stream-id. The requester-id to stream-id mapping is based on PCI-LUT table initialization. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pcie-layerscape: Initialize pci-lut for NXP chasis-2 socsBharat Bhushan
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3 and have similar PCI-Lut. Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: Fixup device tree node for ls2088aHou Zhiqiang
LS2088A and its variants have different PCIe node than LS2080A. The compatible string is updated accordingly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: add LS2088A series SoC pcie supportHou Zhiqiang
The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: enable PCIe config readyHou Zhiqiang
In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-26pci: correct a function descriptionHou Zhiqiang
In the description of function pci_match_one_id(), there are some problems on arguments list and return value description, so correct them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-03-23mvebu: pcie: Add support for GPIO reset for PCIe deviceKonstantin Porotchkin
Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-08dm: core: Replace of_offset with accessorSimon Glass
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-06x86: Don't try to run the VGA BIOS in 64-bit modeSimon Glass
This is not supported, so disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>