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path: root/drivers/pci
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2019-05-20mpc83xx: Make distinct caddy2 configMario Six
vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier. Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20vme8349: Migrate to CONFIG_TARGET_VME8349Mario Six
CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC834*Mario Six
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-08x86: Support PCI VGA ROM when TPL is usedSimon Glass
When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-23pci: Add boundary check for hose->regionsThierry Reding
Make sure that we don't overflow the hose->regions array, otherwise we would end up overwriting the hose->region_count field and cause mayhem to ensue. Also print an error message when we'd be overflowing because it indicates that there aren't enough regions available and the number needs to be increased. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-19pci: pci_mvebu: Add comment about missing of_n_addr_cells() callStefan Roese
This patch adds a comment to explain the use of the hardcoded value for the number of address cells in mvebu_get_tgt_attr(). This should help to rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in general. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-20pci: Don't export pci_hose_config_device()Simon Glass
This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-11pcie: designware: mvebu: fix reset release polarityBaruch Siach
The dm_gpio_set_value() routine sets signal logical level, with GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1 (asserted), while reset inactive value is 0 (de-asserted). Fix the reset toggle code to set the correct reset logic value. Reported-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-05Merge git://git.denx.de/u-boot-marvellTom Rini
- Move Armada XP / 38x PCIe driver to DM_PCI from me - Move Armada XP / 38x LCD driver to DM_VIDEO from me - Add uDPU board (Armada-3720) from Vladimir [trini: Fix warning in pci-uclass.c by removing ret from pci_uclass_child_post_bind as it no longer calls functions with a return code to catch.] Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfigStefan Roese
This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addrStefan Roese
This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-01-17pci: layerscape: Add the dts fixup for EP and RCXiaowei Bao
Add the dts fixup when PCI controller work diffferent mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17pci: layerscape: Do not scan when PEX work in EP modeXiaowei Bao
Don't scan the bus when the PEX work in EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17pci: layerscape: Modify the EP and RC mode judge methodXiaowei Bao
Modify the RC and EP mode judge method, save the mode as a variable, the variable will be used by other function. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-03video: Allow driver to specify the line lengthSimon Glass
At present line_length is always calculated in video_post_probe(). But some hardware may use a different line length, e.g. with a 1366-wide display. Allow the driver to set this value if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-11-20dm/pci: Change the first CFG read to Vendor ID in enumerationHou Zhiqiang
As the PCIe specification recommend reading the Vendor ID register to determine if a Function is present, read the Vendor ID of a non-existent Function must not result in system error, so we'd better make the first CFG read to Vendor ID instead of Header Type register in the PCIe enumeration. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-14dm: pci: Add APIs to find next capability and extended capabilityBin Meng
This introduces two new APIs dm_pci_find_next_capability() and dm_pci_find_next_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device starting from a given offset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-20pci: Support parsing PCI controller DT subnodesMarek Vasut
The PCI controller can have DT subnodes describing extra properties of particular PCI devices, ie. a PHY attached to an EHCI controller on a PCI bus. This patch parses those DT subnodes and assigns a node to the PCI device instance, so that the driver can extract details from that node and ie. configure the PHY using the PHY subsystem. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-09pci: Add a little more debugging to pci_romSimon Glass
Add some logging on failure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-10Remove <inttypes.h> includes and PRI* usages in printf() entirelyMasahiro Yamada
In int-ll64.h, we always use the following typedefs: typedef unsigned int u32; typedef unsigned long uintptr_t; typedef unsigned long long u64; This does not need to match to the compiler's <inttypes.h>. Do not include it. The use of PRI* makes the code super-ugly. You can simply use "l" for printing uintptr_t, "ll" for u64, and no modifier for u32. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28pci: rmobile: Filter out device 1 and 2Marek Vasut
Only PCI device 1 and 2 is populated on the R-Car Gen2 internal PCIe controller. Ignore all other devices. This fix prevents a duplication of OHCI controller response on slot 0 and 1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-08-13Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-08-08FSL PCI: Configure PCIe reference ratioJoakim Tjernlund
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured. This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-08dm: pci: Add APIs to find capability and extended capabilityBin Meng
This introduces two new APIs dm_pci_find_capability() and dm_pci_find_ext_capability() to get PCI capability address and PCI express extended capability address for a given PCI device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08pci: sandbox: emul: Rename priv structureBin Meng
We have "struct sandbox_pci_priv" in pci_sandbox driver. To avoid confusion, rename the emul's priv to "struct sandbox_pci_emul_priv". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08pci: sandbox: Support dynamically binding device driverBin Meng
At present all emulated sandbox pci devices must be present in the device tree in order to be used. The real world pci uclass driver supports pci device driver matching, and we should add such support on sandbox too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08dm: pci: Assign correct driver data when binding a driverBin Meng
The correct driver data comes from the matching 'id' instead of 'find_id' in pci_find_and_bind_driver(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08pci: sandbox: emul: Fix the call to pci_bus_find_devfn()Bin Meng
With the newly added test cases for PCI configuration access, we get: => ut dm pci_busdev Test: dm_test_pci_busdev: pci.c test/dm/pci.c:49, dm_test_pci_busdev(): SANDBOX_PCI_VENDOR_ID == vendor: Expected 4660, got 65535 Test: dm_test_pci_busdev: pci.c (flat tree) test/dm/pci.c:49, dm_test_pci_busdev(): SANDBOX_PCI_VENDOR_ID == vendor: Expected 4660, got 65535 Failures: 2 The bug only shows up when bus number is not equal to zero. This is caused by the plain find_devfn parameter is passed to function call pci_bus_find_devfn(), inside which find_devfn is compared to devfn in the device's pplat structure. However pplat->devfn does not carry the bus number. Fix this by passing find_devfn with bus number masked. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08dm: pci: Fix scanning multi-function deviceBin Meng
The flag to control whether to scan multi-function device during enumeration should be cleared at the beginning of each iteration if the device's function number equals to zero. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08dm: pci: Extract vendor/device id in child_post_bind()Bin Meng
Currently only devfn is extracted in child_post_bind(). Now that we have the live-tree version API to look up PCI vendor and device id from the compatible string, let's extract and save them too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13dm: pci: Use a 1:1 mapping for bus <-> phy addressesChristian Gmeiner
If U-Boot gets used as coreboot payload all pci resources got assigned by coreboot. If a dts without any pci ranges gets used the dm is not able to access pci device memory. To get things working make use of a 1:1 mapping for bus <-> phy addresses. This change makes it possible to get the e1000 U-Boot driver working on a sandybridge device where U-Boot is used as coreboot payload. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed 'u-boot' in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13dm: pci: Make ranges dt property optionalChristian Gmeiner
If we use U-Boot as coreboot payload with a generic dts without any ranges specified we fail in pci pre_probe and our pci bus is not usable. So convert decode_regions(..) into a void function and do the simple error handling there. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed 'u-boot' in the commit message and checkpatch warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resourcesTuomas Tynkkynen
Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: Add newlines to debug prints in pci_auto_common.cTuomas Tynkkynen
All of the debug output from this file is squished to one line. Fix it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not setTuomas Tynkkynen
Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with the 'highmem=off' parameter passed to QEMU's virt machine. The reason is that when 'highmem' is not disabled, QEMU appends 64-bit a memory resource to the PCI controller's regions property in DT in addition to the 32-bit PCI memory window in low memory. And the current DT parsing code picks the last (thus the 64-bit one) memory resource, whose address eventually gets silently truncated to 32 bits because CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break. Avoid this problem by ignoring memory regions whose addresses are above the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-10pci: tegra: introduce weak tegra_pcie_board_port_reset() functionMarcel Ziswiler
Introduce a weak tegra_pcie_board_port_reset() function by default calling the existing tegra_pcie_port_reset() function. Additionally add a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe port index if required. This allows overriding the PCIe port reset functionality from board specific code as e.g. required for Apalis T30 and Apalis TK1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-05-08pci: Don't use pci_indirect when DM is activeMario Six
Declaration of indirect PCI bridges is not compatible with DM: Both define PCI operations, but in different ways. Hence, don't use indirect bridges if DM is active. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-08pci: intel: Add Intel FPGA PCIe controller driverLey Foon Tan
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in rootport mode only, the EP mode is not supported. The driver is tested with the Intel e1000e NIC driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-16pci: video: Only print out when everything is OKBin Meng
If video initialization fails, the "Video:" output message will be mixed with the next console log. Change to print out such message only when everything is OK, which improves the boot log readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30Merge git://git.denx.de/u-boot-marvellTom Rini
2018-03-30arm64: a37xx: pci: add support for aardvark pcie driverWilson Ding
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30dm: pcie: designware: add correct ATU handlingIgal Liberman
Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30dm: pci: Avoid setting a PCI region that has 0 sizeBin Meng
It makes no sense to set a PCI region that has 0 size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30dm: pci: Check board information pointer in decode_regions()Bin Meng
PCI enumeration may happen very early on an x86 board. The board information pointer should have been checked in decode_regions() as its space may not be allocated yet. With this commit, Intel Galileo board boots again. Fixes: 664758c ("pci: Fix decode regions for memory banks") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-05libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>Masahiro Yamada
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones. This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h> Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-23pci: Fix decode regions for memory banksBernhard Messerklinger
Since memory banks may not be located behind each other we need to add them separately. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2018-01-27pci: rmobile: Add RCar Gen2 PCIe controller driverMarek Vasut
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs. The PCIe on Gen2 is used both to connect external PCIe peripherals as well as access the on-SoC USB EHCI controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-01-12drivers: pci: imx: fix enumeration logic errorKoen Vandeputte
By default, the subordinate is set equally to the secondary bus (1) when the RC boots, and does not alter afterwards. This means that theoretically, the highest bus reachable downstream is bus 1. Force the PCIe RC subordinate to 0xff, otherwise no downstream devices will be detected behind bus 1 if the booting OS does not allow enumerating a higher busnr than the subordinate value of the primary bus. Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
generated by cgit (git 2.34.1) at 2024-12-29 04:14:12 +0000