summaryrefslogtreecommitdiff
path: root/drivers/pinctrl
AgeCommit message (Collapse)Author
2019-10-25pinctrl: add support for MediaTek MT7628Weijie Gao
This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-21dm: pinctrl: fix for introduce PINCONF_RECURSIVE optionPatrick Delaunay
Correct the name of the define used CONFIG_IS_ENABLED which is not aligned with Kconfig name: CONFIG_$(SPL_)PINCONF_RECURSIVE. The recursive calls is conditional only for UCLASS_PINCONFIG "pinconfig" driver. It is always needed to call pinctrl_post_bind for UCLASS_PINCTRL "pinctrl", the test CONFIG_IS_ENABLED(PINCONF_RECURSIVE) need to be removed for this driver. This correct a regression introduced because the same patch is applied twice times in u-boot-dm branch: - commit e878b53a79d1 ("dm: pinctrl: introduce PINCONF_RECURSIVE option") - commit c20851b3d850 ("dm: pinctrl: introduce PINCONF_RECURSIVE option") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-21pinctrl: Kconfig: remove duplicated nodesPatrick Delaunay
Remove the duplicated configs introduced when the same patch is applied twice times: - commit e878b53a79d1 ("dm: pinctrl: introduce PINCONF_RECURSIVE option") - commit c20851b3d850 ("dm: pinctrl: introduce PINCONF_RECURSIVE option") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-15dm: pinctrl: introduce PINCONF_RECURSIVE optionPatrick Delaunay
In the Linux pinctrl binding, the pin configuration nodes don't need to be direct children of the pin controller device (may be grandchildren for example). This behavior is managed with the pinconfig u-class which recursively bind all the sub-node of the pin controller. But for some binding (when pin configuration is only children of pin controller) that is not necessary. U-Boot can save memory and reduce the number of pinconf instance when this feature is deactivated (for arch stm32mp for example for SPL). This patch allows to control this feature with a new option CONFIG_PINCONF_RECURSIVE when it is possible for each individual pin controller device. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Fixed CONFIG_IF_ENABLED() condition, added __maybe_unused: Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-15dm: pinctrl: Skip not associated gpio phandle and rise a warning messageMichael Trimarchi
Skip not associated gpio phandle let register the other gpios on a group. We need anyway to send out a warning to the user to fix their uboot-board.dtsi. Thhe handle id can be found inside the decompiled dtb dtc -I dtb -O dts -o devicetree.dts spl/u-boot-spl.dtb Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15dm: pinctrl: introduce PINCONF_RECURSIVE optionPatrick Delaunay
In the Linux pinctrl binding, the pin configuration nodes don't need to be direct children of the pin controller device (may be grandchildren for example). This behavior is managed with the pinconfig u-class which recursively bind all the sub-node of the pin controller. But for some binding (when pin configuration is only children of pin controller) that is not necessary. U-Boot can save memory and reduce the number of pinconf instance when this feature is deactivated (for arch stm32mp for example for SPL). This patch allows to control this feature with a new option CONFIG_PINCONF_RECURSIVE when it is possible for each individual pin controller device. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-08pinctrl: nxp: DM_FLAG_PRE_RELOC by defaultIgor Opaniuk
For NXP SoCs we have to set pinmux configuration ASAP (ideally before relocation) to get serial console working. Without this we miss almost the half of output (U-boot version, CPU defails, Reset cause, DRAM details etc.). To achieve this we need to force appropriate pinctrl drivers to get probed before relocation. Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to dtb/dm") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-08pinctrl: imx: use devfdt_get_addr_size_indexPeng Fan
fdtdec_get_addr_size could not parse addr/size correctly is using address-cells 2 and size-cells 2 on an ARM32 SoC. So switch to use devfdt_get_addr_size_index. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-09-05clk: aspeed: Add support for SD clockEddie James
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-08-27pinctrl: stmfx: update pinconf settingsPatrick Delaunay
Alignment with kernel driver. According to the following tab (coming from STMFX datasheet), updates have to done in stmfx_pinctrl_conf_set function: -"type" has to be set when "bias" is configured as "pull-up or pull-down" -PIN_CONFIG_DRIVE_PUSH_PULL should only be used when gpio is configured as output. There is so no need to check direction. DIR | TYPE | PUPD | MFX GPIO configuration ----|------|------|--------------------------------------------------- 1 | 1 | 1 | OUTPUT open drain with internal pull-up resistor ----|------|------|--------------------------------------------------- 1 | 1 | 0 | OUTPUT open drain with internal pull-down resistor ----|------|------|--------------------------------------------------- 1 | 0 | 0/1 | OUTPUT push pull no pull ----|------|------|--------------------------------------------------- 0 | 1 | 1 | INPUT with internal pull-up resistor ----|------|------|--------------------------------------------------- 0 | 1 | 0 | INPUT with internal pull-down resistor ----|------|------|--------------------------------------------------- 0 | 0 | 1 | INPUT floating ----|------|------|--------------------------------------------------- 0 | 0 | 0 | analog (GPIO not used, default setting) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27pinctrl: pinctrl_stm32: cosmetic: Reorder include filesPatrice Chotard
Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-09pinctrl: renesas: Add R8A77980 V3H PFC tablesMarek Vasut
Import R8A77980 V3H PFC tables from Linux 5.2.7 , commit 5697a9d3d55f. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-07-30Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
2019-07-29pinctrl: mediatek: fix warningFabien Parent
Fix the following warning when CONFIG_PINCONF=n: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:35:36: warning: ‘mtk_drive’ defined but not used [-Wunused-const-variable=] static const struct mtk_drive_desc mtk_drive[] = { ^~~~~~~~~ Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-07-29pinctrl: renesas: fix R-Car gpio0_00 operation fails with 'gpio -input' commandtitron
Fix GPIO bank 0 pin 0 request/release off by one error. Without this patch, it is not possible to request/release GPIO bank 0 pin 0. Signed-off-by: Tiezhuang Dong <tiezhuang.dong.yh@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-07-23pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2Eugeniu Rosca
In spite of the summary line, U-Boot commits [1-2] seem to have aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since they also imported the Linux 5.1 commits listed in [3]. What current commit tries to accomplish is to align the Gen2 and Gen3 pinctrl tables to Linux v5.2. Importing these updates in two steps as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult due to Linux commits like [5-6] which atomically update both Gen2/3 platforms and whose breakdown would not be easily possible. The detailed list of Linux commits squashed into this U-Boot patch is shown in [4]. The second column in [4] depicts the patch id mismatch between the original Linux and the resulted U-Boot commit. The exclamation mark means that manual conflict resolution was involved during cherry picking Linux commit into U-Boot repository (this is mainly caused by dropped changes in files like pfc-r8a7795-es1.c and pfc-r8a77980.c which are missing in U-Boot). This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and boot-tested on: - H3-ES2.0-Salvator-X - M3-ES1.1-Salvator-XS - M3N-ES1.1-ULCB [1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0") [2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0") [3] Linux 5.1 commits already contained in [1-2]: 79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions 729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions 16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions 86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3 b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups 81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions 08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions 99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions 85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins" f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability 5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering 3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering 7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2 699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0 [4] Linux 5.2 commits backported and squashed into this U-Boot patch Linux commit id Linux commit summary line 9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length 5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time 1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers 3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions 2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro 69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro 19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields 360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation 943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2 5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions 662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin 624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C} e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data 0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions [5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro") [6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-19pinctrl: mxs: Add support for i.MX2[38] mxs pinctrl driverLukasz Majewski
The code responsible for setting proper values in the MUX registers (in the mxs_pinctrl_set_state()) has been ported from Linux kernel - SHA1: 17bb763e7eaf tag v5.1.11 from linux-stable. As the pinctrl node in the imx28.dtsi file has gpio pins nodes as subnodes, it was necessary to use 'dm_scan_fdt_dev()' (as a .bind method) to also make them 'visible' by the DM's "gpio_mxs" driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-14Merge tag 'u-boot-stm32-20190712' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - syscon: add support for power off - stm32mp1: add op-tee config - stm32mp1: add specific commands: stboard and stm32key - add stm32 mailbox driver - solve many stm32 warnings when building with W=1 - update stm32 gpio driver
2019-07-13pinctrl: pinctrl-single: Add 'pinctrl-single, bits' supportAdam Ford
The TI Davinci (da850/l138/am1808) use pinctrl-single,bits for pinmuxing peripherals. This patch allosw the pinctrl-single driver to parse the pinctrl-single,bits options and correctly setup devices. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-12pinctrl: stm32: update .bind callbackPatrice Chotard
Update .bind callback in order to bind all pinctrl subnodes with "gpio-controller" property to gpio_stm32 driver. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12pinctrl: pinctrl_stm32: Fix warnings when compiling with W=1Patrick Delaunay
This patch solves the following warnings: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (*idx < 0) ^ drivers/pinctrl/pinctrl_stm32.c: At top level: warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes] int stm32_pinctrl_probe(struct udevice *dev) ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-06-29pinctrl: uniphier: Add SPI pin-mux settingsKunihiko Hayashi
Add pin-mux settings for SPI controller. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-12Merge tag 'u-boot-amlogic-20190612' of git://git.denx.de/u-boot-amlogicTom Rini
- pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groups - pinctrl: meson-gxbb: add hdmi related pins to fix HDMI on GXBB - pinctrl: meson: add support for getting pinmux status - pinctrl: meson-g12a: add support for drive-strength-microamp property
2019-06-12pinctrl: meson-gxbb: add hdmi related pinsMaxime Jourdan
The GXBB pinctrl is missing pins related to HDMI, namely hot plug detection (hpd) and I2C (sda + scl). This fixes HDMI support for GXBB in u-boot. Reported-by: Mohammad Rasim <mohammad.rasim96@gmail.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Mohammad Rasim <mohammad.rasim96@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson: g12a: add DS bank valueGuillaume La Roque
add drive-strength bank regiter and bit value for G12A SoC Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson: add support of drive-strength-microampGuillaume La Roque
drive-strength-microamp is a new feature needed for G12A SoC. the default DS setting after boot is usually 500uA and it is not enough for many functions. We need to be able to set the drive strength to reliably enable things like MMC, I2C, etc ... Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson-axg: add support for getting pinmux statusNeil Armstrong
In order to support the "pinmux status" command, use the common functions to get the pins count and names, and add the AXG specific function to get the current function from registers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson-gx: add support for getting pinmux statusNeil Armstrong
In order to support the "pinmux status" command, use the common functions to get the pins count and names, and add the GX specific function to get the current function from registers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Maxime Jourdan <mjourdan@baylibre.com>
2019-06-12pinctrl: meson: add common function to get pins nameNeil Armstrong
In order to support the "pinmux status" command, add common function to get pins count and pin name. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-12pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groupsNeil Armstrong
The GPIO_TEST_N was in the wrong pmx group table, move it back with the AO groups, GPIODV_18 was missing, add it back, and finally the GPIOCLK_* group names were missing. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-06-11pinctrl: imx: Define imx6_pinctrl_soc_info in .data sectionLukasz Majewski
This commit is necessary to be able to re-use the pinctrl code in early SPL to properly configure pins. The problem is that those "static" structures (without explicit initialization) are placed in the SDRAM area, which corresponds to u-boot proper (not even SPL). Hence, when one wants to configure pins before relocation via DTS/DM, the board hangs (imx6q SoC powered one) as only OCRAM area is available (0x009xxxxx). This commit prevents from this issue by moving the imx6_pinctrl_soc_info structure to data section (from BSS). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-05-08pinctrl: rockchip: Also move common set_schmitter func into per Soc fileDavid Wu
Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Clean the unused type and labelDavid Wu
As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pullDavid Wu
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_pull() func into per SocDavid Wu
As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strengthDavid Wu
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_drive() func into per SocDavid Wu
As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomuxDavid Wu
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Split the common set_mux() into per SocDavid Wu
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Remove redundant spacesDavid Wu
Some files have the redundant spaces, remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08pinctrl: rockchip: Add pull-pin-default param and remove unused paramDavid Wu
Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"Kever Yang
This reverts commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2. This is a superseded version, revert this to apply new patch set. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-07pinctrl: renesas: Add RZ/A1 R7S72100 pin control driverMarek Vasut
Add pin control driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04pinctrl: renesas: Remove sh_pfc_config_mux_for_gpio()Marek Vasut
This function is now replaced by common pin controller GPIO configuration functionality, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Implement gpio_request_enable/gpio_disable_freeMarek Vasut
Implement the gpio_request_enable/gpio_disable_free callbacks to let the GPIO driver call the pin control framework and let it reconfigure pins as GPIOs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: renesas: Set pin type in sh_pfc_config_mux_for_gpioMarek Vasut
Add missing cfg->type = PINMUX_TYPE_GPIO upon successfully setting pin as a GPIO to retain the pin configuration information. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-04pinctrl: gpio: Add callback for configuring pin as GPIOMarek Vasut
Add callback to configure, and de-configure, pin as a GPIO on the pin controller side. This matches similar functionality in Linux and aims to replace the ad-hoc implementations present in U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alex Kiernan <alex.kiernan@gmail.com> Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick DELAUNAY <patrick.delaunay@st.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org>
2019-05-01Merge tag 'rockchip-for-2019.07' of git://git.denx.de/u-boot-rockchipTom Rini
Improvements and new features: - improved SPI driver for better read throughput - refactors initialisation of debug UART init - restructures header file paths - adds pinctrl improvements Adds Kever as a co-custodian.
2019-05-01Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imxTom Rini
Porting to DM and i.MX8 ------------------------ - warp7 to DM - kp_imx53 to DM - Warnings in DT - MX8QM support - colibri-imx6ull to DM - imx7d-pico to DM - ocotp for MX8
2019-05-01pinctrl: exit pinconfig_post_bind if there are no subnodesUrja Rannikko
This fixes RK3288 SPL hanging or hitting this assert: drivers/core/ofnode.c:183: ofnode_first_subnode: Assertion `ofnode_valid(node)' failed. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
generated by cgit (git 2.34.1) at 2024-12-29 04:48:49 +0000