| Age | Commit message (Collapse) | Author |
|---|
|
The new debug() changes pointed out debug code that rotted a little.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
The new speed will be applied by spi_claim_bus.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
This moves the last piece from the old spi_flash driver to the new SPI
framework -- optional DMA RX support. This typically cuts speeds by ~40%
at the cost of additional ~300 bytes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Linux uses an offset of 8 to switch from hardware cs to a gpio cs,
so have u-boot use the same value. Also make sure it is public
for boards to access.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Rather than only support the pins dedicated as chip selects, utilize the
gpio framework to support any gpio pin.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Rather than bang MMRs directly, use the new portmux framework to handle
the details.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
If the requested clock cannot be exactly obtained, round it up so that we
err on the side of slightly slower rather than slightly faster.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Some SPI devices like to see high idle values rather than low.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a
peripheral in order to work.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Blackfin SPI driver was not driving the SPI chip-select high before
putting the chip-select signals into tri-state mode. This is probably
something that slipped by unnoticed in most designs. If the signals are
put directly into a tri-state mode, then the board is relying on the
pull-up resistors to pull up the chip-select before the next transaction.
Most of the time this is fine, except when you have two transactions that
follow each other very closely, such as the flash erase and read status
register commands. In this case I was seeing a 500ns separation between
the transactions. In my setup, with a 10kOhm pull-up, it would meet
timing spec about half the time and resulted in intermittent errors. (A
stronger pull up would fix this, but our design is targeted for low power
consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.)
I modified the spi_cs_deactivate() function in bfin_spi.c to drive the
chip-selects high before putting them into tri-state. For me, this
resulted in a rise time of 5ns instead of the previous rise time of about
1us, and fully satisfied the timing spec of the chip.
Signed-off-by: Todor I Mollov <tmollov@ucsd.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality),
then there is no PORTJ_FER register for us to worry about.
Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
This fills out the SPI backend for the Blackfin on-chip SPI peripheral.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
