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This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
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These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.
In the end we will have:
1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only
All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.
Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
^
This patch is using one variable to do conversion via u32 variable.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
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During spi transfer, for example:
sspi 1:1.0 8 ff
the rx_len values will be:
rx_len = 0
rx_len = 4294967295
This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
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Extend compatible list table for cdns,spi-r1p6 compatible string.
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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GENMASK macro used on zynq_spi.c and zynq_qspi.c
GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
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Used BIT macro on zynq_spi.c and zynq_qspi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
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- Removed unneeded inclusion of header files
- Add "Xilinx" on license text
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
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Store cs value into private data and use it while activating
chipselect instead of passing through function.
Signed-off-by: Jagan Teki <jteki@openedev.com>
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Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK
for more readable.
Signed-off-by: Jagan Teki <jteki@openedev.com>
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Update the numerical values for baudrate and chipselect
with config reg shift named macro's
Signed-off-by: Jagan Teki <jteki@openedev.com>
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priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
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This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
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Trivial fix.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
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This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
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Removed the unnecessary error check from spi_xfer
as the bitlen zero is possible now to deassert the
chip select for which no data is required to be transfered.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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