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path: root/drivers/spi
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2016-01-24dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24spi: ich: Separate out the read/write trace from normal debuggingSimon Glass
The trace is seldom useful for basic debugging. Allow it to be enabled separately so that it is easier to see the more important init and error debug messages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-21rockchip: spi: Remove the explicit pinctrl settingSimon Glass
The correct pinctrl is handled automatically so we don't need to do it in the driver. The exception is when we want to use a different chip select (other than 0). But this isn't used at present. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: spi: Correct chip-enable codeSimon Glass
At present there is an incorrect call to rkspi_enable_chip(). It should be disabling the chip, not enabling it. Correct this and ensure that the chip is disabled when releasing the bus. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: spi: Implement the delaysSimon Glass
Some devices need delays before and after activiation. Implement these features in the SPI driver so that we will be able to enable the Chrome OS EC. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: spi: Correct the bus init codeSimon Glass
Two of the init values are created locally so cannot be out of range. The masking is unnecessary and in one case is incorrect. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: spi: Remember the last speed to avoid re-setting itSimon Glass
Rather than changing the clock to the same value on every transaction, remember the last value and don't adjust the clock unless it is necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: spi: Avoid setting the pinctrl twiceSimon Glass
If full pinctrl is enabled we don't need to manually set the pinctrl in the driver. It will happen automatically. Adjust the code to suit - we will still use manual mode in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21rockchip: spi: Update the driver to use the new clock IDSimon Glass
We can use the new clk_get_by_index() function to get the correct clock. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20spi: ti_qspi: Use 4-byte opcode for mmap readVignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB. Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB. Signed-off-by: Ravi Babu <ravibabu@ti.com> [vigneshr@ti.com: Re-word commit description] Signed-off-by: Vignesh R <vigneshr@ti.com>
2016-01-19spi: rk_spi: Fix debug format warningTom Rini
We need to use %lx not %x to describe a fdt_addr_t Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19Add more SPDX-License-Identifier tagsTom Rini
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-14spi: kirkwood_spi.c: Add driver model supportStefan Roese
This patch adds driver model support to the kirkwood SPI driver. Which is also used on the MVEBU SoC's, now being converted to DM. Non-DM support is still available for the "older" platforms using this driver, like kirkwood. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
2016-01-14spi: kirkwood_spi.c: Prepare for driver model supportStefan Roese
This patch prepares the Kirkwood SPI driver, also used on the MVEBU board (Armada XP / 38x), for the conversion to driver model. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
2016-01-13drivers: spi: ti_qspi: convert driver to adopt device driver modelMugunthan V N
adopt ti_qspi driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-01-13spi: Add support for dual and quad modeMugunthan V N
spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13drivers: spi: ti_qspi: prepare driver for DM conversionMugunthan V N
Prepare driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-01-13drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model ↵Mugunthan V N
conversion Changing the ti_qspi_priv structure and its instance names from to priv for driver mode conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-01-13drivers: spi: ti_qspi: do not hard code chip select for memory map configurationMugunthan V N
To enable memory map in dra7xx, specific chip select must be written to control module register. But this hard coded to chip select 1, fixing it by writing the specific chip select value to control module register. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-01-13spi: Rename op_mode_rx to mode_rxJagan Teki
Since spi rx mode macro's are renamed to simple and meaninfull, this patch will rename the respective structure members. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13spi: Rename SPI_OPM_RX_* to SPI_RX_*Jagan Teki
SPI_OPM_RX_AS - SPI_RX_SLOW SPI_OPM_RX_AF - SPI_RX_FAST SPI_OPM_RX_DOUT - SPI_RX_DUAL SPI_OPM_RX_QOF - SPI_RX_QUAD Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUADJagan Teki
Since SPI_TX_* are spi_slave{} members so use spi protocol notation instead spi flash programming, like SPI_TX_BP => SPI_TX_BYTE SPI_TX_QPP => SPI_TX_QUAD Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-13spi: Use mode instead of op_mode_txJagan Teki
Used mode member from spi_slave{} instead of op_mode_tx. Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-01-07spi: fsl_qspi: fix an error of using GENMASKGong Qianyu
This commit fixes the change of below commit "spi: fsl_qspi: Use GENMASK" (sha1 :bad490a24212c068c5b718b9189f47ea4075d078) Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-18spi: zynq_qspi: Add configuration to disable LQSPI featureNathan Rossi
When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-15fsl_qspi: Pet the watchdog while reading/writingAlexander Stein
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-11spi: xilinx: Add new compatible stringsMichal Simek
Add xlnx,xps-spi-2.00.a/b which is compatible string listed in the Linux kernel. Remove origin one which has no real background. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-11spi: Kconfig: Fix correct target name for ZynqMPMichal Simek
ZynqMP is using different symbol. Use correct one. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11spi: zynq_spi: Add cadence compatible stringMichal Simek
Extend compatible list table for cdns,spi-r1p6 compatible string. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-11spi: ti_qspi: Fix SPI_3WIRE checking using modeJagan Teki
SPI_3WIRE is spi mode not spi flags, so this patch fixed the spi-3wire checking throgh mode instead of flags. Cc: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11spi: Get spi-3wire from dtsJagan Teki
spi-3wire is used when SI/SO signals shared so get the same from dts node and assign to mode on slave plat->mode. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-11-19Move console definitions into a new console.h fileSimon Glass
The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2015-11-19dm: spi: Add support for all targets which requires MANUAL_RELOCMichal Simek
It is follow up patch based on "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) to update function pointers for DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-18altera_spi: change ioremap to map_physmemThomas Chou
Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-17spi: ti_qspi: Add dummy readl for bus syncVignesh R
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-12Tegra: T210: Add QSPI driverTom Warren
This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-06spi: altera_spi: minor clean upThomas Chou
- Remove the penultimate comma in of_match ids Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05spi: cadence_qspi: Ensure check for max frequency in placeChin Liang See
Ensure the intended SCLK frequency not exceeding the maximum frequency. If that happen, SCLK will set to maximum frequency. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2015-11-05spi: cadence_qspi: Fix fdt read of spi-max-frequencyChin Liang See
Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2015-11-05spi: cadence_qspi: Ensure spi_calibration is run when sclk changeChin Liang See
Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-28Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2015-10-28spi: altera_spi: Minor cleanupJagan Teki
- Moved macro definitions to top - Give tab space to CONFIG_ALTERA_SPI_IDLE_VAL value - Re-arrange header includes ascending order Acked-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-28spi: altera_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in altera_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Marek Vasut <marex@denx.de> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27Merge git://git.denx.de/u-boot-dmTom Rini
2015-10-27spi: xilinx_spi: Use GENMASKJagan Teki
Replace numeric mask hexcodes with GENMASK macro in xilinx_spi Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: tegra: Use GENMASKJagan Teki
Replace numeric mask hexcodes with GENMASK macro in tegra*.c Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: omap3_spi: Use GENMASKJagan Teki
Replace numeric mask hexcodes with GENMASK macro in omap3_spi Cc: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: fsl_qspi: Use GENMASKJagan Teki
Replace numeric mask hexcodes with GENMASK macro in fsl_qspi Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: designware_spi: Use GENMASKJagan Teki
Replace numeric mask hexcodes with GENMASK macro in designware_spi Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
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