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path: root/drivers/spi
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2019-04-12spi: cadence_qspi: Add quad write supportLey Foon Tan
Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-03-04spi: Rename sun4i_spi.c into spi-sunxi.cJagan Teki
Now the same SPI controller driver is reusable in all Allwinner SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c which eventually look like a common sunxi driver. Also update the function, variable, structure names in driver from sun4i into sunxi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4i: Driver cleanupJagan Teki
- drop unused macros. - use base instead of base_addr, for better code readability - move .probe and .ofdata_to_platdata functions in required places to add platdata support in future. - use sentinel sun4i_spi_ids. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4: Add A31 spi controller supportJagan Teki
The usual SPI transmission protocol in Allwinner A10 and A31 controllers share similar context with minimal changes in register offsets along with few additional register bits on A31. So, add A31 spi controller support in existing sun4i_spi with A31 specific register offsets and bits. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4i: Add CLK supportJagan Teki
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver. Clock disablement could be done while releasing the bus transfer, but the existing code doesn't disable the clocks it only taken care of clock enablement globally in probe. So to make a proper clock handling, the clocks should enable it in claim and disable it in release. This patch would also do that change, by enable and disable clock in proper order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: sun4i: Support fifo_depth via drvdataJagan Teki
Support fifo_depth via drvdata instead of macro definition, this would eventually reduce another macro definition for new SPI controller fifo depth support addition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: sun4i: Access registers and bits via enum offsetsJagan Teki
Allwinner support two different SPI controllers one for A10 and another for A31 with minimal changes in register offsets and respective register bits, but the logic for accessing the SPI master via SPI slave remains nearly similar. Add enum offsets for register set and register bits, so-that it can access both classes of SPI controllers. Assign same control register for global, transfer and fifo control registers to make the same code compatible with A31 SPI controller. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
2019-03-04spi: sun4i: Simplify reg writes using set/clrbits_le32Jagan Teki
Update the existing register writes using setbits_le32 and clrbits_le32 in required places. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4i: Poll for rxfifo to be filled upJagan Teki
To drain rx fifo the fifo need to poll for how much data has been filled up in rx fifo. To achieve this, the current code is using wait_for_bit logic on control register with exchange burst mode mask, which is not a proper way of waiting for fifo filled up. So, add code for polling rxfifo to be filled up using fifo status register. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: designware: Change include orderHoratiu.Vultur@microchip.com
With current order of include files, the file designware_spi.c can't see that the struct global_data has the member board_type when CONFIG_BOARD_TYPES is defined. By not seeing this then all the members are shifted in the struct global_data. So when the driver is trying to read from device tree blob, it would pass the wrong address to the function 'fdtdev_get_int'. This will make to use the default frequency 500000. The fix consists of changing the order of include files in designware_spi.c to include first common.h file. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-28spi: omap3: fix set_wordlen() reading from incorrect address for CHCONFDavid Rivshin
_omap3_spi_set_wordlen() indexed the regs->channel[] array with the old wordlen (instead of the chipselect number) when reading the current CHCONF register value. This meant it read from the wrong memory location, modified that value, and then wrote it back to the correct CHCONF register. The end result is that most slave configuration settings would be lost, such as clock divisor, clock/chipselect polarities, etc. Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin <drivshin@allworx.com>
2019-02-14spi: zynqmp_gqspi: Enable versal compatible stringMichal Simek
Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-07configs: Don't use SPI_FLASH_BAR as defaultVignesh R
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: Switch to new SPI NOR frameworkVignesh R
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD layer. Fix up sf_dataflash to work in legacy way. And update sandbox to use new interfaces/definitions Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: Add non DM version of SPI_MEMVignesh R
Add non DM version of SPI_MEM to support easy migration to new SPI NOR framework. This can be removed once DM_SPI conversion is complete. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: spi-mem: Claim SPI bus before spi mem accessVignesh R
It is necessary to call spi_claim_bus() before starting any SPI transactions and this restriction would also apply when calling spi-mem operations. Therefore claim and release bus before requesting transfer via exec_op. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer sizeVignesh R
Extend spi_mem_adjust_op_size() to take spi->max_write_size and spi->max_read_size into account. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modesVignesh R
SPI controllers support all types of SPI modes including dual/quad bus widths. Therefore remove constraint wrt SPI mode from spi-mem layer. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-01-28spi: mxc_spi: Fix build warning on ARM64 platformsYe Li
When building mxc_spi driver on ARM64 platforms, get below build warnings. Fix it in this patch. In file included from include/common.h:48:0, from drivers/spi/mxc_spi.c:9: drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’: drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-16mips: spi: mscc: Add fast bitbang SPI driverLars Povlsen
This patch add a new SPI driver for MSCC SOCs that does not sport the designware SPI hardware controller. Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-02spi: sun4i: Add rx_buf NULL pointer checkStefan Mavrodiev
Current driver doesn't check if the destination pointer is NULL. This cause the data from the FIFO to be stored inside the internal SDRAM ( address 0 ). The patch add simple check if the destination pointer is NULL. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Jagan Teki <jagan@openedev.com> [jagan: fix commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-12-19DW SPI: Allow to overload the management of the external CSGregory CLEMENT
On some platforms, as the Ocelot ones, when wanting to control the CS through software, it is not possible to do it through the GPIO controller. Indeed, this signal is managed through a dedicated range of registers inside the SoC.. By declaring the external_cs_manage function as weak, it is possible to manage the CS at platform level and then using the appropriate registers. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-05Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- Various MTD fixes from Boris - Zap various unused / legacy paths. - pxa3xx NAND update from Miquel Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-03spi, mpc8xx: migrate to DM_SPIChristophe Leroy
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-11-29spi: cadence_qspi: use "cdns,qspi-nor" as compatibleSimon Goldschmidt
Linux uses "cdns,qspi-nor" as compatible string for the cadence qspi driver, so change driver, docs and all device trees. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-27spi: mpc8xx: Migrate to DM_SPIChristophe Leroy
Drop non-dm code and migrate into DM_SPI. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [jagan: Move config menu in DM_SPI area] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27spi: Remove unused spi_initJagan Teki
Remove spi_init definition which never used on respective code since from many years. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27dm: platform_data: spi: s/pl022_spi.h/spi_pl022.hJagan Teki
Rename platform_data include file as spi_pl022.h from pl022_spi.h, this is generic notation used for spi platdata include files. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27spi: pl022: Drop unnecessary include filesJagan Teki
This patch can drop unnecessary include files in pl022_spi driver. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27spi: pl022: Simplify platdata codeJagan Teki
pl022 spi driver support both OF_CONTROL and PLATDATA, this patch is trying to simplify the code that differentiating platdata vs of_control. - Move OF_CONTROL code at one place - Handle clock setup code directly in pl022_spi_ofdata_to_platdata Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-24spi: mtk_qspi: add qspi driver for MT7629 SoCGuochun Mao
This patch adds MT7629 qspi driver for accessing SPI NOR flash. Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-24spi: Add Amlogic Meson SPI Flash Controller driverNeil Armstrong
The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. This driver, ported from the Linux meson-spi-spifc driver, add support for this controller on the Amlogic Meson GX SoCs in U-Boot. Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-20dm: spi: prevent setting a speed of 0 HzSimon Goldschmidt
When the device tree is missing a correct spi slave description below the bus (compatible "spi-flash" or spi-max-frequency are missing), the 'set_speed' callback can be called with 'speed' == 0 Hz. At least with cadence qspi, this leads to a division by zero. Prevent this by initializing speed to 100 kHz in this case (same fallback value as is done in 'dm_spi_claim_bus') and issue a warning to console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-16arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-12Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2018-10-10spi: davinci: Add platdata supportJagan Teki
Davanci spi driver has DM support already, this patch add support for platdata so-that SPL can use it for low foot-print. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com>
2018-10-09dm: spi: Add logging of some return valuesSimon Glass
When SPI flash operations fail it is helpful to be able to see the error codes and where they are generated. Add logging to capture this information for read operations. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09sandbox: spi: Add more loggingSimon Glass
Add logging to aid debugging features in these drivers. Also drop some code in sandbox_spi_xfer() which is not used. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-04spi: Add SPI driver for MT76xx SoCsStefan Roese
This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1. Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Piotr Dymacz <pepe2k@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-10-02Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-02spi: sh_qspi: Add DM support to SH QSPI driverMarek Vasut
Add DM support to the SH QSPI driver while retaining non-DM support. The later is required as this driver is used in SPL which has a size limitation of 16 kiB. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> [jagan: use proper commit head] Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-02driver/spi: fsl_qspi: Remove non-DM stuffAshish Kumar
Convert fsl_qspi.c to complete DM mode. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Tested-by: Rajat Srivastava <rajat.srivastava@nxp.com> Tested-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-02spi: designware_spi: Add reset ctrl to driverLey Foon Tan
Add code to reset all reset signals as in SPI DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Release reset when _remove(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-09-25spi: add support for ARM PL022 SPI controllerQuentin Schulz
This adds support for the ARM PL022 SPI controller for the standard variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX FIFO. A few parts were borrowed from the Linux kernel driver. Cc: Armando Visconti <armando.visconti@st.com> Cc: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-20spi: Extend the core to ease integration of SPI memory controllersBoris Brezillon
Some controllers are exposing high-level interfaces to access various kind of SPI memories. Unfortunately they do not fit in the current spi_controller model and usually have drivers placed in drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI memories in general. This is an attempt at defining a SPI memory interface which works for all kinds of SPI memories (NORs, NANDs, SRAMs). Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-08-03arm: sunxi: Allwinner A10 SPI driverStefan Mavrodiev
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-08-03spi: kirkwood: add orion-spi compatible stringChris Packham
This matches the compatible string used by the Linux kernel. This will allow u-boot to use the same device tree files. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: use armada instead of orion on .data] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-03spi: kirkwood: Get drvdata in .ofdata_to_platdataJagan Teki
Get the is_errata_50mhz_ac in .ofdata_to_platdata, and reuse it in .set_mode this can eventually initialized dt code at once and adding room to add platdata. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-23spi: stm32_qspi: rework mode managementChristophe Kerello
This patch solves quad read issue with Macronix/Micron spi nor. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-07-23spi: stm32_qspi: assign functional operation mode in _stm32_qspi_gen_ccrChristophe Kerello
This patch assigns the functional operation mode in _stm32_qspi_gen_ccr function. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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