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path: root/drivers/spi
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2018-03-15Merge git://git.denx.de/u-boot-spiTom Rini
2018-03-14spi: omap3: Fix redeclared errorJagan Teki
omap3_spi_set_speed|mode redeclared bus symbol, fix the same. error: drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’: drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol struct udevice *bus = dev->parent; Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13board: stm32: switch to DM STM32 timerPatrice Chotard
Use available DM stm32_timer driver instead of dedicated mach-stm32/stm32fx/timer.c. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx Enable DM STM32_TIMER for STM32F4/F7 and H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13spi: omap3: Skip set_mode, set_speed from claimJagan Teki
set_mode, set_seed functions has separate function pointers in dm_spi_ops, so use them in relevent one instead of calling from claim_bus. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13spi: atcspi200: Drop non-dm codeJagan Teki
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig already enabled DM_SPI, so non-dm code make no use of it hence droped. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-02-13spi: Migrate CONFIG_CF_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_KIRKWOOD_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_LPC32XX_SSP to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MPC8XXX_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MXC_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MXS_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_SH_QSPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_SH_SPI to KconfigTuomas Tynkkynen
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-07atcspi200: avoid possible NULL dereferenceHeinrich Schuchardt
Check if ns before and not after dereferencing it. Indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-01-26Merge git://git.denx.de/u-boot-spiTom Rini
2018-01-26DW SPI: Get clock value from Device TreeEugeniy Paltsev
Add option to set spi controller clock frequency via device tree using standard clock bindings. Define dw_spi_get_clk function as 'weak' as some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API and implement dw_spi_get_clk their own way in their clock manager. Get rid of clock_manager.h include as we don't use cm_get_spi_controller_clk_hz function anymore. (we use redefined dw_spi_get_clk in SOCFPGA clock managers instead) Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: cadence_qspi_apb: Make flash writes 32 bit alignedVignesh R
Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 bit aligned buffers. This is required because as per TI K2G TRM[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer. Otherwise indirect writes is known to fail sometimes. [1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when ↵Vignesh R
possible" This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. Using bounce_buf.c to handle non-DMA alignment problems is bad as bounce_buf.c does cache manipulations which is not required. Therefore revert this patch in favour of local bounce buffer solution in the next patch. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when ↵Goldschmidt Simon
possible" This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates the data cache after reading. This is meant for dma transfers only and breaks the cadence_qspi driver which copies via cpu only: data that is copied by the cpu is in cache only and the cache invalidation at the end throws away this data. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: cadence_spi: Sync DT bindings with LinuxJason Rush
Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-24spi: kirkwood_spi: implement workaround for FE-9144572Chris Packham
Erratum NO. FE-9144572: The device SPI interface supports frequencies of up to 50 MHz. However, due to this erratum, when the device core clock is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and CPOL=CPHA=1 there might occur data corruption on reads from the SPI device. Implement the workaround by setting the TMISO_SAMPLE value to 0x2 in the timing1 register. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: spi-uclass: Fix style violationsMario Six
Remove a superfluous newline, and reduce the scope of a variable. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Remove spi_setup_slave_fdtMario Six
A previous patch removed the spi_flash_probe_fdt function, which contained the last call of the spi_setup_slave_fdt function, which is now equally obsolete. This patch removes the function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Remove obsolete spi_base_setup_slave_fdtMario Six
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node") added a helper function spi_base_setup_slave_fdt to to set up a SPI slave from a given FDT blob. The only user was the exynos SPI driver. But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed the use of this function, hence rendering it obsolete. Remove this function, as well as the CONFIG_OF_SPI option, which guarded only this function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Fix style violation and improve codeMario Six
This patch fixes a printf specifier style violation, reduces the scope of a variable, and turns a void pointer that is used with pointer arithmetic into a u8 pointer. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dm: spi: add BCM63xx HSSPI driverÁlvaro Fernández Rojas
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dm: spi: add BCM63xx SPI driverÁlvaro Fernández Rojas
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-22Convert CONFIG_DAVINCI_SPI to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_DAVINCI_SPI Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-12spi: fsl_qspi: support i.MX6UL/6ULLL/7DPeng Fan
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size. The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly. Add the compatible entry for 6ul/7d. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-11-30cosmetic: atcspi200: Rename function name as atcspi200Rick Chen
Integrate function and struct name from ae3xx to atcspi200 will be more reasonable. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spiRick Chen
atcspi200 is Andestech spi ip which is embedded in AE3XX and AE250 platforms. So rename as atcspi200 will be more reasonable to be used in different platforms. Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-21rockchip: spi: the symbol for Hertz is HzHeinrich Schuchardt
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-20omap3: spi: the symbol for Hertz is HzHeinrich Schuchardt
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-10-27spi: ich: Lock down controller settings if requiredBin Meng
Some Intel FSP (like Braswell) does SPI lock-down during the call to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, it's bootloader's responsibility to configure the SPI controller's opcode registers properly otherwise SPI controller driver doesn't know how to communicate with the SPI flash device. Rather than passively doing the opcode configuration, let's add a simple DTS property "intel,spi-lock-down" and let the driver call the opcode configuration function if required by such FSP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-16spi: Drop CONFIG_ATMEL_DATAFLASH_SPITuomas Tynkkynen
Last user of this option went away in commit: fdc7718999 ("board: usb_a9263: Update to support DT and DM") Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-10-04treewide: replace with error() with pr_err()Masahiro Yamada
U-Boot widely uses error() as a bit noisier variant of printf(). This macro causes name conflict with the following line in include/linux/compiler-gcc.h: # define __compiletime_error(message) __attribute__((error(message))) This prevents us from using __compiletime_error(), and makes it difficult to fully sync BUILD_BUG macros with Linux. (Notice Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().) Let's convert error() into now treewide-available pr_err(). Done with the help of Coccinelle, excluing tools/ directory. The semantic patch I used is as follows: // <smpl> @@@@ -error +pr_err (...) // </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Re-run Coccinelle] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29spi: davinci_spi: Add da830-spi support for DMAdam Ford
The DM support is already in the driver, so add da830-spi to the compatible list. Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-25spi: fsl_qspi: Copy 16 byte aligned data in TX FIFOSuresh Gupta
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25spi: fsl_qspi: Add controller busy check before new spi operationSuresh Gupta
It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25spi: mxc_spi: support driver modelPeng Fan
Add driver model support for mxc spi driver. Most functions are restructured to be reused by DM and non-DM. Tested on mx6slevk/mx6qsabresd board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-21nds32: spi: Support spi dm driver.rick
Support spi driver and can detect MX25U1635E flash on AE3XX board. Verification: sf probe 0:0 50000000 0 spi_flash_std_probe(sf_Probr.c) spi_flash_probe_slave(sf_Probr.c) SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB NDS32 # sf test 0x100000 0x1000 SPI flash test: 0 erase: 34 ticks, 117 KiB/s 0.936 Mbps 1 check: 15 ticks, 266 KiB/s 2.128 Mbps 2 write: 21 ticks, 190 KiB/s 1.520 Mbps 3 read: 11 ticks, 363 KiB/s 2.904 Mbps Test passed 0 erase: 34 ticks, 117 KiB/s 0.936 Mbps 1 check: 15 ticks, 266 KiB/s 2.128 Mbps 2 write: 21 ticks, 190 KiB/s 1.520 Mbps 3 read: 11 ticks, 363 KiB/s 2.904 Mbps Signed-off-by: rick <rick@andestech.com>
2017-09-18rockchip: spi: Convert to livetreePhilipp Tomsich
Update the Rockchip SPI driver to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-02x86: ich-spi: Clear atomic preop only when SPI settings are not lockedBin Meng
The atomic preop register can only be written when SPI settings are not locked, otherwise it's read-only. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02x86: ich-spi: Remove useless assignment in ich_spi_xfer()Bin Meng
In ich_spi_xfer() when the driver presets control fields, control variable gets assigned twice. Apparently only the last assignment takes effect. Remove the other one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Move opcode registers configuration to another routineBin Meng
At present the ICH SPI opcode registers configuration is done in the ich_spi_remove() routine, a little bit weird but that's how current. Linux MTD driver works. This changes to move the opcode registers configuration to a separate routine ich_spi_config_opcode() which might be called by U-Boot itself as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Don't read cached lock statusBin Meng
At present the ICH SPI controller driver reads the controller lock status from its register in the probe routine and saves the lock status to a member of priv. Later the driver uses the cached status from priv to judge whether the controller setting is locked and do different setup. But such logic is only valid when there is only the SPI controller driver that touches the SPI hardware. In fact the lock status change can be trigged outside the driver, eg: during the fsp_notify() call when Intel FSP is used. This changes the driver to read the lock status every time when an SPI transfer is initiated instead of reading the cached one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Remove unnecessary assignment in ich_init_controller()Bin Meng
There is no need to do another assignment to ich7_spi. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24x86: ich-spi: Remove spi_write_protect_region()Bin Meng
This routine is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-14Merge branch 'master' of git://git.denx.de/u-boot-rockchipTom Rini
generated by cgit (git 2.34.1) at 2024-12-28 20:43:11 +0000