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path: root/drivers/spi
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2020-06-01spi: Zap sh_spi driverJagan Teki
sh_spi driver is deprecated, no active updates and no board user, hence dropped the same. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Kconfig: Move MSCC_BB_SPI, FSL_QSPI into DM_SPIJagan Teki
- MSCC_BB_SPI - FSL_QSPI Both are fully dm-driven, let's move them into DM_SPI side definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Kconfig: Drop redundant CF_SPI definitionJagan Teki
CF_SPI kconfig option defined twice with DM_SPI and non DM_SPI. Drop the non DM_SPI side kconfig definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi Drop spi_init()Jagan Teki
spi_init doesn't exist anywhere in the code. Drop it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/bug.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop image.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop bootstage.h from common headerSimon Glass
Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-15rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOODTrevor Woerner
Have this symbol follow the pattern of all other such symbols. This patch also removes a TODO from the code. Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-11spi: nxp-fspi: Use new readl_poll_sleep_timeout APIKuldeep Singh
Board gets reset when performing burst read/write operations. On the other hand, no such behaviour is observed on small size operations. In Linux, readl_poll_timeout API already adds delay of 1us which is further skipped in U-boot. Hence, use new "readl_poll_sleep_timeout" API which adds delay alongwith timeout functionality. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-05-11spi: Zap lpc32xx_ssp driver-related codeJagan Teki
lpc32xx_ssp driver is deprecated, no active updates and no board user, hence dropped the same. Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.aribaud@3adev.fr> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30spi: sifive: Fix QPP transferJagan Teki
The guessed reason is that the existing logic of filling tx fifo with data, rx fifo with NULL for tx transfer and filling rx fifo with data, tx fifo with NULL for rx transfer is not clear enough to support the Quad Page Program.     SiFive SPI controllers have specific sets of watermark registers and SPI I/O directions bits in order to program SPI controllers clear enough to support all sets of operating modes.     Here is the exact programing sequence that would follow on this patch and tested via SPI-NOR and MMC_SPI.     - set the frame format proto, endian - set the frame format dir, set it for tx and clear it for rx - TX transfer:   fill tx fifo with data.   wait for TX watermark bit to clear. - RX transfer:   fill tx fifo with 0xff.   write nbytes to rx watermark register   wait for rx watermark bit to clear.   read the rx fifo data. So, this patch adopts this program sequence and fixes the existing I/O direction bit. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Fix format register proto fieldJagan Teki
SiFive SPI controller has a proto bit field in frame format register which would be used to configure the SPI I/O protocol lines used on specific transfer.  Right now the driver is configuring this proto using slave->mode, for all types of transctions. This makes the driver unable to function since the proto needs to configure dynamically for each and every transaction separately at runtime. Now, the controller driver supports per transfer via spi-mem exec_opo, so add the fmt_proto flag and fill the per transfer buswidth so that the controller configures the proto bit at runtime. This patch fixes the SPI controller works with SPI NOR flash on quad read with page program. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Add spi-mem exec opJagan Teki
SiFive SPI controller is responsible to handle the slave devices like mmc spi and spi nor flash. The controller is designed such a way that it would handle the slave transactions based on the I/O protocol numbers, example if spi nor slave send quad write opcode it has to send alone with I/O protocol number of 4 and if it try to send data it has to send I/O protocol number along with 4 line data. But the current spi-xfer code from spi-mem is combining the opcode and address in a single transaction, so the SPI controller will be unable to identify the I/O protocol number of opcode vs address. So, add the spi-mem exec_op with spi-xfer of opcode, address and data as a separate transaction. This doesn't remove the .xfer of dm_spi_ops since mmc spi will make use of it. Note: This code might have moved to the spi-mem core area once we have done the dedicated tests on other controllers and have real reason to move. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Tidy up dm_spi_slave_platdata variableJagan Teki
Usually variable name slave is used for spi_slave structure and slave_plat for the dm_spi_slave_platdata. Let's follow this meaningful notation by replacing slave with slave_plat for dm_spi_slave_platdata structure. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-29spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enumTudor Ambarus
Commit: 0ebb261a0b2d ("spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum") in linux. When defining spi_mem_op templates we don't necessarily know the size that will be passed when the template is actually used, and basing the supports_op() check on op->data.nbytes to know whether there will be data transferred for a specific operation is not possible. Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum so that we can base our checks on op->data.dir instead of op->data.nbytes. This also fixes a bug identified with the atmel-quaspi driver. The spi-nor core, when erasing sectors, fills the spi_mem_op template using SPI_MEM_OP_NO_DATA, which initializes all the data members with value zero. This is wrong because data.dir is treated as SPI_MEM_DATA_IN, which translates in our driver to read accesses for erases (RICR), while the controller expects write accesses (WICR). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29spi: cadence-qspi: Move ref clock calculation to probePratyush Yadav
"assigned-clock-parents" and "assigned-clock-rates" DT properties take effect only after ofdata_to_platdata() when clk_set_defaults() is called in device_probe(). Therefore clk get rate() would return a wrong value in ofdata_to_platdata() when compared with probe. Hence it needs to be moved to probe. Tested on u-boot-ti/next. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29spi: Transform the FSL QuadSPI driver to use the SPI MEM APIKuldeep Singh
To support the SPI MEM API, instead of modifying the existing U-Boot driver, this patch adds a port of the existing Linux driver. This also has the advantage that porting changes and fixes from Linux will be easier. Porting of driver left most of the functions unchanged while few of the changes are: -Remove lock(mutexes) and irq handler as u-boot is a single core execution. -Remove invalid masterid as it was required specially for multicore execution in LS2088ARDB which is not the case in u-boot. -Remove clock support as changing spi speed is not supported in uboot and nor in linux. Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY, LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-24spi: mpc8xxx_spi: fix missing dev_err definitionRasmus Villemoes
The build currently fails with drivers/spi/mpc8xxx_spi.c:64:3: warning: implicit declaration of function ‘dev_err’ [-Wimplicit-function-declaration] ... drivers/spi/built-in.o: In function `mpc8xxx_spi_set_speed': drivers/spi/mpc8xxx_spi.c:227: undefined reference to `dev_err' Fixes: 4856cc7a97 (mpc8xxx_spi: implement real ->set_speed) Fixes: 1a7b462dee (mpc8xxx_spi: put max_cs to use) Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-04-03Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegraTom Rini
- Add support for Jetson Nano, plus miscellaneous other fixes found during Nano bringup. - Add Igor's update_uboot wrapper patches.
2020-04-02qspi: t210: Use dev_read calls to get FDT data like base, freqTom Warren
This Tegra QSPI driver hadn't been brought up to date with how DM drivers are fetching data from the FDT now, and was pulling in bogus data for base, max freq, etc. Fixed ofdata_to_platdata to work the same way it does in the tegra114 SPI driver, using dev_read_ functions. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02qspi: t210: Fix QSPI clock and tap delaysTom Warren
When claim_bus was setting the clock, it reset the QSPI controller, which wipes out any tap delays set by previous bootloaders (nvtboot, CBoot for example on Nano). Instead of doing that in claim_bus, which gets called a lot, moved clock setting to probe(), and set tap delays there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env save works reliably again. Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02qspi: t210: Fix claim_bus's use of the wrong bus/deviceTom Warren
claim_bus() is passed a udevice *dev, which is the bus device's parent. In this driver, claim_bus assumed it was the bus, which caused the 'priv' info pointer to be wrong, and periph_id was incorrect. This in turn caused the periph clock call to assign the wrong clock (PLLM instead of PLLP0), which caused a kernel warning. I only saw the 'bad' periph_id when enabling DEBUG due to an assert. Not sure how QSPI was working w/this errant clock, but it was moot as QSPI wasn't active unless you probed it, and that wasn't happening until I posted a patch to enable env save to QSPI for Nano (coming soon). Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02spi: atmel-quadspi: Add verbose debug facilities to monitor register accessesTudor Ambarus
This feature should not be enabled in release but can be useful for developers who need to monitor register accesses at some specific places. Helped me identify a bug in u-boot, by comparing the register accesses from the u-boot driver with the ones from its linux variant. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> [jagan: use 16 bit array with tmp variable] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-02spi: atmel-quadspi: fix possible MMIO window size overrunTudor Ambarus
The sama5d2 QSPI controller memory space is limited to 128MB: 0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000. There are nor flashes that are bigger in size than the memory size supported by the controller: Micron MT25QL02G (256 MB). Check if the address exceeds the MMIO window size. An improvement would be to add support for regular SPI mode and fall back to it when the flash memories overrun the controller's memory space. Fixes: 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-03-31mpc8xxx_spi: implement real ->set_speedRasmus Villemoes
Not all boards have the same CSB frequency, nor do every SPI slave necessarily support running at 16.7 MHz. So implement ->set_speed; that also allows using a smaller PM (i.e., 0) for slaves that do support a higher speed. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31mpc8xxx_spi: always use 8-bit characters, don't read or write garbageRasmus Villemoes
There are a few problems with the current driver. First, it unconditionally reads from dout/writes to din whether or not those pointers are NULL. So for example a simple "sf probe" ends up writing four bytes at address 0: => md.l 0x0 8 00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ => sf probe 0 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48 SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB => md.l 0x0 8 00000000: ff000000 45454545 05050505 05050505 ....EEEE........ 00000010: 00000000 00000000 07070707 07070707 ................ (here I've change the first debug statement to a printf, and made it print the din/dout pointers rather than the uints they point at). Second, as we can also see above, it always writes a full 32 bits, even if a smaller amount was requested. So for example => mw.l $loadaddr 0xaabbccdd 8 => md.l $loadaddr 8 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ 02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x400 6 device 0 offset 0x400, size 0x6 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48 SF: 6 bytes @ 0x400 Read: OK => sf read 0x02000010 0x400 8 device 0 offset 0x400, size 0x8 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64 SF: 8 bytes @ 0x400 Read: OK => md.l $loadaddr 8 02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE.......... 02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........ Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7 bytes), the last three bytes and up being the wrong ones, since the driver does a full 32 bit read and then shifts the wrong byte out: => mw.l $loadaddr 0xaabbccdd 4 => md.l $loadaddr 4 02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................ => sf read $loadaddr 0x444 10 device 0 offset 0x444, size 0x10 mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128 SF: 16 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0 => mw.l $loadaddr 0xaabbccdd 4 => sf read $loadaddr 0x444 0xb device 0 offset 0x444, size 0xb mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40 mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88 SF: 11 bytes @ 0x444 Read: OK => md.l $loadaddr 4 02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219...... Fix all of that by always using a character size of 8, and reject transfers that are not a whole number of bytes. While it ends being more work for the CPU, we're mostly bounded by the speed of the SPI bus, and we avoid writing to the mode register in every loop. Based on work by Klaus H. Sørensen. Cc: Klaus H. Sorensen <khso@prevas.dk> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31mpc8xxx_spi: put max_cs to useRasmus Villemoes
Currently, max_cs is write-only; it's just set in mpc8xxx_spi_ofdata_to_platdata and not otherwise used. My mpc8309 was always resetting during an "sf probe 0". It turns out dm_gpio_set_dir_flags() was being called with garbage, since nothing had initialized priv->gpios[0] - our device tree used "cs-gpios" rather than "gpios", so gpio_request_list_by_name() had returned 0. That would have been a lot easier to figure out if the chip select index was sanity checked, so rename max_cs to cs_count, and reject a xfer with a too large cs index. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-02-05dm: core: Drop the inclusion of linux/compat.h in dm.hSimon Glass
Most files don't need this header and it pulls in quite of lots of stuff, malloc() in particular. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-04spi: ich: Drop while loop in hardware sequencing erase caseWolfgang Wallner
When ich_spi_exec_op_hwseq() is called to erase a 4k block (opcode = SPINOR_OP_BE_4K), it expects to find a length value in op->data.nbytes, but that value is always 0. As a result, the while loop is never executed and no erase is carried out. Fix this by dropping the loop code entirely, only keeping the relevant parts of the loop body. See http://patchwork.ozlabs.org/patch/1222779/ for more detailed background information and discussion. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-27spi: cadence-qspi: Add compatible for TI AM654Vignesh Raghavendra
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add support for Cadence Octal SPI controllerVignesh Raghavendra
Cadence OSPI is similar to QSPI IP except that it supports Octal IO (8 IO lines) flashes. Add support for Cadence OSPI IP with existing driver using new compatible Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27mtd: spi-nor-core: Add octal mode supportVignesh Raghavendra
Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence-qspi: Add direct mode supportVignesh Raghavendra
Add support for Direct Access Controller mode of Cadence QSPI. This allows MMIO access to SPI NOR flash providing better read performance. Direct mode is only exercised if AHB window size is greater than 8MB. Support for flash address remapping is also not supported at the moment and can be added in future. For better performance, driver uses DMA to copy data from flash in direct mode using dma_memcpy(). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: cadence_qspi: Move to spi-mem frameworkVignesh Raghavendra
Current Cadence QSPI driver has few limitations. It assumes all read operations to be in Quad mode and thus does not support SFDP parsing. Also, adding support for new mode such as Octal mode would not be possible with current configuration. Therefore move the driver over to spi-mem framework. This has added advantage that driver can be used to support SPI NAND memories too. Hence, move driver over to new spi-mem APIs. Please note that this gets rid of mode bit setting done when CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to that config option. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: ti_qspi: Add support for CS other than CS0Vignesh Raghavendra
Make sure corresponding setup registers are updated depending on CS. This ensures that driver can support QSPI flashes on ChipSelects other than on CS0 Reported-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27spi: prevent overriding established bus settingsMarcin Wojtas
The SPI stack relies on a proper bus speed/mode configuration by calling dm_spi_claim_bus(). However the hitherto code allowed to accidentally override those settings in the spi_get_bus_and_cs() routine. The initially established speed could be discarded by using the slave platdata, which turned out to be an issue on the platforms whose slave maximum supported frequency is not on par with the maximum frequency of the bus controller. This patch fixes above issue by configuring the bus from spi_get_bus_and_cs() only in case it was not done before. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27dm: spi: Check cs number before accessing slavesBin Meng
Add chip select number check in spi_find_chip_select(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
2020-01-27spi: nxp_fspi: new driver for the FlexSPI controllerMichael Walle
This is a port of the kernel's spi-nxp-fspi driver. It uses the new spi-mem interface and does not expose the more generic spi-xfer interface. The source was taken from the v5.3-rc3 tag. The port was straightforward: - remove the interrupt handling and the completion by busy polling the controller - remove locks - move the setup of the memory windows into claim_bus() - move the setup of the speed into set_speed() - port the device tree bindings from the original fspi_probe() to ofdata_to_platdata() There were only some style change fixes, no change in any logic. For example, there are busy loops where the return code is not handled correctly, eg. only prints a warning with WARN_ON(). This port intentionally left most functions unchanged to ease future bugfixes. This was tested on a custom LS1028A board. Because the LS1028A doesn't have proper clock framework support, changing the clock speed was not tested. This also means that it is not possible to change the SPI speed on LS1028A for now (neither is it possible in the linux driver). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-01-23spi: bcm63xx-hsspi: allow to use this driver on arm bcm68360Philippe Reynes
This IP is also used on some arm SoC, so we allow to use it on arm bcm68360 too. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-17common: Move clock functions into a new fileSimon Glass
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-14spi: Fix manual relocation calling more timesAshok Reddy Soma
When two instances of AXI QSPI with flash are added and tested simultaneously the spi driver operations are relocated twice. As a result code is accessing addresses outside of RAM when relocated second time which is causing a crash. Tested on Microblaze. Similar change was done in past by: commit f238b3f0fbc9 ("watchdog: dm: Support manual relocation for watchdogs") commit 2588f2ddfd60 ("dm: sf: Add support for all targets which requires MANUAL_RELOC") commit 1b4c2aa25bdf ("gpio: dm: Support manual relocation for gpio") Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-06Merge branch 'next'Tom Rini
Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
2019-12-27spi: rk: Limit transfers to (64K - 1) bytesJagan Teki
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-15spi: ich: Add Apollo Lake supportSimon Glass
Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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