summaryrefslogtreecommitdiff
path: root/drivers/timer
AgeCommit message (Collapse)Author
2017-11-30atcpit100: timer: Remove arch dependency.Rick Chen
ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30cosmetic: atcpit100_timer: Use device api to get platdataRick Chen
Use dev_get_platdata to get private platdata. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30cosmetic: atcpit100_timer: Rename function name as atcpit100Rick Chen
Integrate function and struct name as atcpit100 will be more reasonable. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30ae3xx: timer: Rename AE3XX to ATCPIT100Rick Chen
ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-30ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.Rick Chen
It will be work fine with unsigned long declaretion in timer register struct when system is 32 bit. But it will not work well when system is 64 bit. Replace it by u32 and verify both ok in 32/64 bit. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-06sti: fix STMicroelectronics copyrightPatrice Chotard
Uniformize all STMicroelectronics copyrights headers for STi related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-09-18rockchip: timer: update for 32/64bit-aware OF_PLATDATAPhilipp Tomsich
With dtoc emitting fdt64_t for addresses (and region sizes), the array indices for accessing the reg[] array needs to be adjusted. This adjusts the Rockchip DM timer driver to correctly handle OF_PLATDATA given this new structure layout. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-18rockchip: timer: Convert to livetreePhilipp Tomsich
Update the Rockchip timer driver to support a live device tree. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18rockchip: timer: implement timer_get_boot_usPhilipp Tomsich
To make the Rockchip DM timer driver useful for the timing of bootstages, we need a few enhancements: - This implements timer_get_boot_us. - This avoids reinitialising the timer, if it has already been set up (e.g. by our TPL and SPL stages). Now, we have a single timebase ticking from TPL through the full U-Boot. - This adds support for reading the timer even before the device-model is ready: we find the timer via /chosen/tick-timer, then read its address and clock-frequency, and finally read the timeval directly). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18dm: timer: handle being called before dm_root is readyPhilipp Tomsich
When used with bootstage recording, dm_timer_init may be called surprisingly early: i.e. before dm_root is ready. To deal with this case, we explicitly check for this condition and return -EAGAIN to the caller (refer to drivers/timer/rockchip_timer.c for a case where this is needed/used). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18dm: timer: Convert to livetreePhilipp Tomsich
This updates dm_timer_init to support a live tree and deals with some fallout (i.e. the need to restructure the code such, that we don't need multiple discontinuous #if CONFIG_IS_ENABLED blocks). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-16dm: x86: Allow TSC timer to be used before DM is readySimon Glass
With bootstage we need access to the timer before driver model is set up. To handle this, put the required state in global_data and provide a new function to set up the device, separate from the driver's probe() method. This will be used by the 'early' timer also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16x86: tsc: Add Airmont reference clock valuesBin Meng
Per the Intel 64 and IA-32 Architecture Software Developer's Manual, add the reference clock for Intel Atom Processors based on the Airmont Microarchitecture (Braswell). This keeps in sync with Linux kernel commit: 6fcb41c: x86/tsc_msr: Add Airmont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-05rockchip: timer: fix U_BOOT_DRIVER namePhilipp Tomsich
When I originally added this driver, I did some careless (and in retrospect: mindless) copy & paste for the U_BOOT_DRIVER structure skeletion... unfortunately, the 'arc_timer' string was committed and slipped through all reviews. This fixes the U_BOOT_DRIVER name to read 'rockchip_rk3368_timer' (as originally intended). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reported-by: Artturi Alm <artturi.alm@gmail.com>
2017-08-26driver: timer: Add the Atmel PIT timer driverWenyou.Yang@microchip.com
Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-13rockchip: timer: add device-model timer driver for RK3368 (and similar)Philipp Tomsich
This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13dm: timer: normalise SPL and TPL supportPhilipp Tomsich
To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13timer: add OF_PLATDATA support for timer-uclassPhilipp Tomsich
The timer-uclass depends on full OF_CONTROL through its interrogation of /chosen and the code to determine the clock-frequency. For the OF_PLATDATA case, these code-paths are disabled and it becomes the timer driver's responsibility to correctly set the clock-frequency in the uclass priv-data. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: kconfig: Select TIMER and X86_TSC_TIMERBin Meng
Without a timer, U-Boot just doesn't boot. This is not something we can turn off. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()Bin Meng
Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that better describes what the routine does. This keeps in sync with Linux kernel commit: 02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: tsc: Correct Silvermont reference clock valuesBin Meng
Atom processors use a 19.2 MHz crystal oscillator. Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz. Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz. Update the Silvermont-based tables accordingly, matching the Software Developers Manual. Also, correct a 166 MHz entry that should have been 116 MHz, and add a missing 80 MHz entry for VLV2. This keeps in sync with Linux kernel commit: 05680e7: x86/tsc_msr: Correct Silvermont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: tsc: Update comments and expand definitions in freq_desc_tables[]Bin Meng
Some processor abbreviations in the comments of freq_desc_tables[] are obscure. This updates part of these to mention processors that are known to us. Also expand frequency definitions. This keeps in sync with Linux kernel commit: 9e0cae9: x86/tsc_msr: Update comments, expand definitions Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()Bin Meng
If either ratio or freq is zero, the return value is zero. There is no need to create a fail branch and return zero there. This keeps in sync with Linux kernel commit: 14bb4e3: x86/tsc_msr: Remove debugging messages Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: tsc: Identify Intel-specific codeBin Meng
try_msr_calibrate_tsc() is currently Intel-specific, and should not execute on any other vendor's parts. This keeps in sync with Linux kernel commit: ba82683: x86/tsc_msr: Identify Intel-specific code Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: tsc: Read all ratio bits from MSR_PLATFORM_INFOBin Meng
Currently we read the tsc radio like this: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f; Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the Intel manual, the ratio bits are bit 8-15. Fix this problem by masking 0xff instead. This keeps in sync with Linux kernel commit: 886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: core: Update lists_bind_fdt() to use ofnodeSimon Glass
Adjust this function to use an ofnode instead of an offset, so it can be used with livetree. This involves updating all callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: core: Replace of_offset with accessor (part 2)Simon Glass
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01dm: Rename dev_addr..() functionsSimon Glass
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-22nds32: Support AE3XX platform.rick
Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
2017-05-22nds32: Support AG101P timer DM.rick
Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
2017-03-24drivers: timer: Introduce ARC timer driverVlad Zakharov
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14STiH410: Add STi timer driverPatrice Chotard
Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-02-08dm: core: Replace of_offset with accessorSimon Glass
At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-28aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com
Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2016-12-27timer: Support clocks via phandleZakharov Vlad
Earlier timer driver needed a clock-frequency property in compatible device-tree nodes. Another way is to reference a clock via a phandle. So now timer_pre_probe tries to get clock by reference through device tree. In case it is impossible to get clock device through the reference, clock-frequency property of the timer node is read to provide backward compatibility. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-14Merge git://git.denx.de/u-boot-dmTom Rini
2016-03-14dm: omap_timer: Fix conversion of address to a pointerLokesh Vutla
OMAP timer driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address instead of a pointer for the uart base") Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-14dm: Use uclass_first_device_err() where it is usefulSimon Glass
Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-26sandbox: timer: Support the early timerSimon Glass
Add support for the early timer so we can use tracing with sandbox again. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-26timer: Provide an early timerSimon Glass
In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-26timer: Support tracing fullySimon Glass
A few of the functions in the timer uclass are not marked with 'notrace'. Fix this so that tracing can be used with CONFIG_TRACE. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20timer: sandbox: work without device treeStephen Warren
A default invocation of sandbox U-Boot apparently uses no device tree, which means that no timer is registers, which in turn means that the sleep shell command hangs. Fix the sandbox timer code to register a device when there's no DT, just like e.g. the sandbox reset driver does. When there's no DT, the DM uclass can't initialize clock_rate from DT, so set a default value in the timer code instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: timer: refuse timers with zero clock_rateStephen Warren
If a timer has a zero clock_rate, get_tbclk() will return zero for it, which will cause tick_to_time() to perform a division-by-zero, which will crash U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20drivers: timer: omap_timer: add timer driver for omap devices based on dmMugunthan V N
Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-01-20dm: timer: uclass: Add flag to control sequence numberingMugunthan V N
Like SPI and I2C, timer devices also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in timer_uclass driver to control device sequence numbering. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: timer: uclass: add timer init in uclass driver to add timer deviceMugunthan V N
Adding timer init function in timer-uclass driver to create and initialize the timer device on platforms where u-boot,dm-pre-reloc is not used. Since there will be multiple timer devices in the system, adding a tick-timer node in chosen node to know which timer device to be used as tick timer in u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-12-09x86: Move i8254_init() to x86_cpu_init_f()Bin Meng
Right now i8254_init() is called from timer_init() in the tsc timer driver. But actually i8254 and tsc are completely different things. Since tsc timer has been converted to driver model, we should find a new place that is appropriate for U-Boot to call i8254_init(), which is now x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01x86: tsc: Move tsc_timer.c to drivers/timerBin Meng
To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01dm: timer: Support 64-bit counterBin Meng
There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Modify timer_get_count() to ask timer driver to always return a 64-bit counter value, and provide an inline helper function timer_conv_64() to handle the 32-bit/64-bit conversion automatically. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01timer: sandbox: Use device tree to pass the clock frequencyBin Meng
We should use device tree to pass the clock frequency of the timer instead of hardcoded in the driver codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-12-27 04:43:20 +0000