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path: root/drivers/video/sunxi/sunxi_dw_hdmi.c
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2019-12-02common: Move get_ticks() function out of common.hSimon Glass
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-09-21sunxi: video: HDMI: Fix LCD clock dividerMark Kettenis
Currently we may end up with an LCD clock divider that differs from the HDMI PHY clock divider if we can't exactly match the pixel clock. Fix this by using DIV_ROUND_UP to calculate the divider. This works since the PLL is chosen such that the resulting pixel clock is never higher than the requested pixel clock. Fixes: 1feed358ed15 ("sunxi: video: HDMI: Fix clock setup") Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-29video: dw_hdmi: Add support for ddc-i2c-bus propertyNiklas Schulze
Add support for the ddc-i2c-bus device tree property which allows for using an external i2c master for reading the display's EDID. Signed-off-by: Niklas Schulze <me@jns.io>
2019-03-28sunxi: video: HDMI: Fix clock setupJernej Skrabec
Currently, HDMI driver doesn't consider minimum and maximum allowed rate of pll3 (video PLL). It works most of the time, but not always. Consider monitor with resolution 1920x1200, which has pixel clock rate of 154 MHz. Current code would determine that pll3 rate has to be set to 154 MHz. However, minimum supported rate is 192 MHz. In this case video output just won't work. The reason why the driver is written in the way it is, is that at the time HDMI PHY and clock configuration wasn't fully understood. But now we have needed knowledge, so the issue can be fixed. With this fix, clock configuration routine uses full range (1-16) for clock divider instead of limited one (1, 2, 4, 11). It also considers minimum and maximum allowed rate for pll3. Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-05-15sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.Vasily Khoruzhick
HSYNC is bit 8, and VSYNC is bit 9. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-12-02sunxi: video: HDMI: split VSYNC and HSYNC polarity settingsVasily Khoruzhick
These are actually different bits, and since some monitors (Benq BL2420PT) have modes with different HSYNC and VSYNC polarity, we should set them independently Tested on Pine64-LTS with Benq BL2420PT monitor. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-28sunxi: video: Add A64/H3/H5 HDMI driverJernej Skrabec
This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>