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Sigend-off-by: Wolfgang Denk <wd@denx.de>
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Driver for the Atmel MACB on-chip ethernet controller.
This driver has been tested on the ATSTK1000 board with a AT32AP7000
CPU. It should probably work on AT91SAM926x as well with some minor
modifications.
Hardware documentation can be found in the AT32AP7000 data sheet,
which can be downloaded from
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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Rewrite the resource management code (i.e. I/O memory, clock gating,
gpio) so it doesn't depend on any global state. This is necessary
because this code is heavily used before relocation to RAM, so we
can't write to any global variables.
As an added bonus, this makes u-boot's memory footprint a bit smaller,
although some functionality has been left out; all clocks are enabled
all the time, and there's no checking for gpio line conflicts.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0)
which is used to se if an slave will ACK after receiving its address.
Correct i2c probing to use this method as the old method could upset
a slave as it wrote a data byte to it.
Add a small delay in i2c_init() to let the controller
shutdown any ongoing I2C activity.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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The problem is not gcc4 but the code itself. The BD_STATUS() macro can't
be used for busy-waiting since it strips the 'volatile' property from
the bd variable. gcc3 was working by pure luck.
This is a follow on patch to "Fix the UEC driver bug of QE"
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I've redone the SBC8349 support to match git-current, which
incorporates all the MPC834x updates from Freescale since the 1.1.6
release, including the DDR changes.
I've kept all the SBC8349 files as parallel as possible to the
MPC8349EMDS ones for ease of maintenance and to allow for easy
inspection of what was changed to support this board. Hence the SBC8349
U-Boot has FDT support and everything else that the MPC8349EMDS has.
Fortunately the Freescale updates added support for boards using CS0,
but I had to change spd_sdram.c to allow for board specific settings for
the sdram_clk_cntl (it is/was hard coded to zero, and that remains the
default if the board doesn't specify a value.)
Hopefully this should be mergeable as-is and require no whitespace
cleanups or similar, but if something doesn't measure up then let me
know and I'll fix it.
Thanks,
Paul.
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This patch supports DUART, ETH3/4 and PCI etc.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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The patch prevents the GCC tool chain from striping useful code for
optimization. It will make UEC ethernet driver workable, Otherwise the
UEC will fail in tx when you are using gcc4.x. but the driver can work
when using gcc3.4.3.
CHANGELOG
*Prevent the GCC from striping code for optimization, Otherwise the UEC
will tx failed when you are using gcc4.x.
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Conflicts:
drivers/Makefile
Fix the merge conflict in file drivers/Makefile
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
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As suggested by Grant Likely this patch enables the Xilinx SystemACE
driver to select 8 or 16bit mode upon startup.
Signed-off-by: Stefan Roese <sr@denx.de>
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Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command
is fully finished. The sync() is defined in each CPU's io.h file. For
those CPUs which do not need sync for now, a dummy sync() is defined in
their io.h as well.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch removes some problems when the Xilinx SystemACE driver
is used with 16bit access on an big endian platform (like the
AMCC Katmai).
Signed-off-by: Stefan Roese <sr@denx.de>
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buffer pointers
Block device read/write is anonymous data; there is no need to use a
typed pointer. void * is fine. Also add a hook for block_read functions
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Register read/write does not need to be wrapped in a full function. The
patch replaces them with macros.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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The code in this file is not a command; it is a device driver. Put it in
the correct place. There are zero functional changes in this patch, it
only moves the file.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Conflicts:
drivers/cfi_flash.c
The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007
fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support
mpc7448hpc2 board.
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if you must swap the bytes between reading/writing.
(Needed for the SC3 board)
Signed-off-by: Heiko Schocher <hs@denx.de>
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The EBC Configuration Register is now by CFG_EBC_CFG definable
Added JFFS2 support for the SC3 board.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Some code cleanup.
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Signed-off-by: Heiko Schocher <hs@denx.de>
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Here the description from Brian Brelsford <Brian_Brelsford@dell.com>:
The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part
returns a 0x15. In the code fragment below bits [1:0] determine the
page size, it is ANDed via "(extid & 0x3)" then shifted out. The
next field is also ANDed with 0x3. However this is a one bit field
as defined in the Hynix and Samsung parts in the 4th ID byte that
determins the oobsize, not a two bit field. It works on Samsung as
bits[3:2] are 01. However for the Hynix there is a 11 in these two
bits, so the oob size gets messed up.
I checked the correct linux code and the suggested fix from Brian is
also available in the linux nand mtd driver.
Signed-off-by: Stefan Roese <sr@denx.de>
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offset to go into CFI mode)
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Signed-off-by: Heiko Schocher <hs@denx.de>
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The conflicts due to a new mpc7448 p3m7448 board is in the main tree.
Merge branch 'master' into hpc2
Conflicts:
MAKEALL
cpu/74xx_7xx/cpu.c
cpu/74xx_7xx/cpu_init.c
cpu/74xx_7xx/speed.c
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(1) remove some C++ comments.
(2) remove trailing white space.
(3) remove trailing empty line.
(4) Indentation by table.
(5) remove {} in one line condition.
(6) add space before '(' in function call.
Remove some weird printf () output.
Add necessary comments.
Modified Makefile to support building in a separate directory.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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Signed-off-by: Timur Tabi <timur@freescale.com>
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give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
since they are passed by reference to ucc_get_cmxucr_reg and assigned.
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Merge branch 'master' into hpc2
Conflicts:
drivers/cfi_flash.c
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Signed-off-by: Stefan Roese <sr@denx.de>
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Two fixes for the nand_wait() function in
drivers/nand/nand_base.c:
1. Use correct timeouts. The original timeouts in Linux
source are 400ms and 20ms not 40s and 20s
2. Return correct error value in case of timeout. 0 is
interpreted as OK.
Signed-off-by: Rui Sousa <rui.sousa@laposte.net>
Signed-off-by: Stefan Roese <sr@denx.de>
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* Adds support for AMD command set Top Boot flash geometry reversal
* Adds support for reading JEDEC Manufacturer ID and Device ID
* Adds support for displaying command set, manufacturer id and
device ids (flinfo)
* Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined
* Removes outdated change history (refer to git log instead)
Signed-off-by: Tolunay Orkun <listmember@orkun.us>
Signed-off-by: Stefan Roese <sr@denx.de>
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Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Signed-off-by: Timur Tabi <timur@freescale.com>
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Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: Timur Tabi <timur@freescale.com>
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this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
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PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006090742000024 "Add support for multiple I2C buses"
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
CHANGELOG:
* Add support for the Freescale MPC8349E-mITX reference design platform.
The second TSEC (Vitesse 7385 switch) is not supported at this time.
Signed-off-by: Timur Tabi <timur@freescale.com>
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