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2019-11-10ram: rk3328: Fix loading of skew valuesSimon South
Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10ram: rk3328: Use correct frequency units in functionSimon South
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10clk: rockchip: rk3328: Configure CPU clockSimon South
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk809: support rk809 pmicJoseph Chen
The RK809 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes) - RTC - Clocking Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk817: support rk817 pmicJoseph Chen
The RK817 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH) - RTC - Clocking Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk805: support rk805 pmicElaine Zhang
The RK805 are a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 3*LDOs) - RTC - Clocking Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: pmic: rk816: support rk816 pmicElaine Zhang
The RK816 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH) - RTC - Clocking Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10power: regulator: rk8xx: update the driver for rk808 and rk818Elaine Zhang
In order to adapt the following pmics, make the interface more compatible. Support buck and ldo suspend voltage setting and getting. Supprot buck and ldo suspend enable/disable setting and getting. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10dm: regulator: support regulator more stateJoseph Chen
support parse regulator standard property: regulator-off-in-suspend; regulator-init-microvolt; regulator-suspend-microvolt: regulator_get_suspend_enable regulator_set_suspend_enable regulator_get_suspend_value regulator_set_suspend_value Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-06Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- DFU updates - USB Storage updates
2019-11-05mmc: fsl_esdhc_imx: Update compatible string for imx8mPeng Fan
To enable HS400(ES) and UHS for imx8m platforms, update the driver data to share with imx8qm esdhc_soc_data. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05mmc: fsl_esdhc_imx: drop redundant clock settingsPeng Fan
During mmc initialization, there are several calls to mmc_set_clock and mmc_set_ios. When mmc_power_off, the mmc->clock will be set, but the imx driver will use 400KHz. So the following calls to mmc_set_ios will set the clock several times which is redundant in fsl_esdhc_imx driver. So let's simplify to remove redundant clock settings. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05mmc: fsl_esdhc: clean up DM and non-DM codeYangbo Lu
Make DM and non-DM code clear using below structure. #if !CONFIG_IS_ENABLED(DM_MMC) <non-DM_MMC code> #else <DM_MMC code> #endif Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05mmc: fsl_esdhc: always check write protect stateYangbo Lu
The QorIQ eSDHC on all platforms supports checking write protect state through register bit. So check it always. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05mmc: fsl_esdhc: drop redundant code for non-removable featureYangbo Lu
Drop redundant code for non-removable feature. "non-removable" property has been read in mmc_of_parse(). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common()Yangbo Lu
The fsl_esdhc_init() was actually to get configuration of mmc_config. So rename it to fsl_esdhc_get_cfg_common() and make it common for both DM_MMC and non-DM_MMC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05mmc: fsl_esdhc: clean up bus width configuration codeYangbo Lu
This patch is to clean up bus width setting code. - For DM_MMC, remove getting "bus-width" from device tree. This has been done in mmc_of_parse(). - For non-DM_MMC, move bus width configuration from fsl_esdhc_init() to fsl_esdhc_initialize() which is non-DM_MMC specific. And fix up bus width configuration to support only 1-bit, 4-bit, or 8-bit. Keep using 8-bit if it's not set because many platforms use driver without providing max bus width. - Remove bus_width member from fsl_esdhc_priv structure. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05mmc: fsl_esdhc: fix voltage validationYangbo Lu
Voltage validation should be done by CMD8. Current comparison between mmc_cfg voltages and host voltage capabilities is meaningless. So drop current comparison and let voltage validation is through CMD8. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init()Yangbo Lu
Controller initialization is not needed in fsl_esdhc_init(). It will be done in esdhc_init() for non-DM_MMC, and in esdhc_init_common() in probe for DM_MMC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-04Merge tag 'u-boot-imx-20191104' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191104 ------------------- - i.MX NAND: nandbcb support for MX6UL / i.MX7 - i.MX8: support for HAB - Convert to DM (opos6ul, mccmon6) - Toradex i.MX6ull colibri - sync DTS with kernel Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416
2019-11-04Merge branch '2019-11-04-ti-imports'Tom Rini
- Various CPSW related improvements, DTS resync
2019-11-04net: ti: cpsw: convert to use dev/ofnode apiGrygorii Strashko
Conver TI CPSW driver to use dev/ofnode api. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> [trini: Add <dm/ofnode.h> to provide the prototype to ofnode] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-03Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Add support for Intel FSP-S and FSP-T in binman - Correct priority selection for image loaders for SPL - Add a size check for TPL - Various small SPL/TPL bug fixes and changes - SPI: Add support for memory-mapped flash
2019-11-03nand: mxs_nand: add API for switching different BCH layoutsIgor Opaniuk
On i.MX7 in a sake of reducing the disturbances caused by a neighboring cells in the FCB page in the NAND chip, a randomizer is enabled when reading the FCB page by ROM bootloader. Add API for setting BCH to specific layout (and restoring it back) used by ROM bootloader to be able to burn it in a proper way to NAND using nandbcb command. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03mach-imx: Adding new argument for SIP call interfaceYe Li
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ, so update the interface to add new argument. Signed-off-by: Ye Li <ye.li@nxp.com> [agust: fixed imx8m-power-domain build] Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03power: pmic: Kconfig: add CONFIG_SPL_DM_PMIC_BD71837Peng Fan
Add CONFIG_SPL_DM_PMIC_BD71837 to make this driver could be used in SPL stage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03pmic: bd71837: drop DEBUG macroPeng Fan
Drop DEBUG macro definition which is used for debug purpose. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03video: mxsfb: set gd->fb_baseSébastien Szymanski
Set gd->fb_base so it can be shown with bdinfo command. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03watchdog: imx: Use immediate reset bits for expire_nowRobert Hancock
The expire_now function was previously setting the watchdog timeout to minimum and waiting for the watchdog to expire. However, this watchdog also has bits to trigger immediate reset. Use those instead, like the Linux imx2_wdt driver does. Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03watchdog: imx: Add DT ext-reset handlingRobert Hancock
The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the device tree to specify whether the board design should use the external reset instead of the internal reset. Use this boolean to determine which mode to use rather than using external reset unconditionally. For the legacy non-DM mode, the external reset is always used in order to maintain the previous behavior. Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid modeGrygorii Strashko
Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping default value (enabled) for MAC TX internal delay when "rgmii-rxid" interface mode is selected. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: fix mac tx internal delay for rgmii-rxid modeGrygorii Strashko
Now TI CPSW driver will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping default value (enabled) for MAC TX internal delay when "rgmii-rxid" interface mode is selected. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: add support for standard eth "max-speed" dt propertyGrygorii Strashko
This patch adds support for standard Ethernet "max-speed" DT property to allow PHY link speed limitation. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: move parsing of dt port's parameters in separate funcGrygorii Strashko
Move parsing of dt port's parameters in separate func for better code readability. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: enable 10Mbps link speed support in rgmii modeGrygorii Strashko
According to TRMs the 10Mbps link speed is supported in RGMII only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_SL_MACCTRL.EXT_EN(18) = 1. Hence update cpsw_slave_update_link() to follow documentation. [1] https://patchwork.kernel.org/patch/10285239/ Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03x86: timer: Use a separate flag for whether timer is initedSimon Glass
At present the value of the timer base is used to determine whether the timer has been set up or not. It is true that the timer is essentially never exactly 0 when it is read. However 'time 0' may indicate the time that the machine was reset so it is useful to be able to denote that. Update the code to use a separate flag instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: timer: Set up the timer in timer_early_get_count()Simon Glass
This function can be called before the timer is set up. Make sure that the init function is called so that it works correctly. This is needed so that bootstage can work correctly in TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03spi: Add support for memory-mapped flashSimon Glass
On x86 platforms the SPI flash can be mapped into memory so that the contents can be read with normal memory accesses. Add a new SPI method to find the location of the SPI flash in memory. This differs from the existing device-tree "memory-map" mechanism in that the location can be discovered at run-time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-01Merge tag 'arc-fixes-for-2020.01-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-arc ARC fixes for v2020.01-rc2 The main change is move to DM_MMC of yet 2 another ARC boards: AXS101 & IoTDK. Among that we improve handling of stock-formatted SD-cards of high volume on EM SDP as well as introduction of reset driver for HSDK which is required for prepser reinitialization of some peripherals like USB etc.
2019-11-01ARC: HSDK: introduce reset driverEugeniy Paltsev
Introduce reset driver for Synopsys ARC HSDK SoC Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-01Merge tag 'efi-2020-01-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-01-rc2 Provide a better user interface for setting UEFI variables. Bug fixes: - ext4 file system not discovered on UEFI block device - 'make tests' build error on 32bit systems
2019-11-01Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dmTom Rini
- Fix for patman with email addresses containing commas - Bootstage improvements for TPL, SPL - Various sandbox and dm improvements and fixes
2019-10-31drivers: phy: Handle gracefully NULL pointersJean-Jacques Hiblot
For some controllers PHYs can be optional. Handling NULL pointers without crashing nor failing, makes it easy to handle optional PHYs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-31ata: ahci allow 64-bit DMA for SATARoman Kapl
Allow 64-bit DMA on AHCI. If not supported by the host controller, at least print a message and fail. Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-10-31nvme: use page-aligned buffer for identify commandPatrick Wildt
Change the stack-allocated buffer for the identification command to explicitly allocate page-aligned buffers. Even though the spec seems to allow having admin queue commands on non page-aligned buffers, it seems to not be possible on my i.MX8MQ board with a a Silicon Power P34A80. Since all of the NVMe drivers I have seen always do admin commands on a page-aligned buffer, which does work on my system, it makes sense for us to do that as well. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31nvme: flush dcache on both r/w, and the prp listPatrick Wildt
It's possible that the data cache for the buffer still holds data to be flushed to memory, since the buffer was probably used as stack before. Thus we need to make sure to flush it also on reads, since it's possible that the cache is automatically flused to memory after the NVMe DMA transfer happened, thus overwriting the NVMe transfer's data. Also add a missing dcache flush for the prp list. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31virtio: pci: use correct type in virtio_pci_bind()Heinrich Schuchardt
For printing as %u we should use an unsigned int. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31usb: ehci-hcd: Keep async schedule runningMarek Vasut
Profiling the EHCI driver shows a significant performance problem in ehci_submit_async(). Specifically, this function keeps enabling and disabling async schedule back and forth for every single transaction. However, enabling/disabling the async schedule does not take effect immediatelly, but instead may take up to 1 mS (8 uFrames) to complete. This impacts USB storage significantly, esp. since the recent reduction of maximum transfer size to support more USB storage devices. This in turn results in sharp increase in the number of ehci_submit_async() calls. Since one USB storage BBB transfer does three such calls and the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB, which is unacceptable. However, this overhead can be removed simply by keeping the async schedule running. Specifically, the first transfer starts the async schedule and then each and every subsequent transfer only adds a new QH into that schedule, waits until the QH is completed and does NOT disable the async schedule. The async schedule is stopped only by shutting down the controller, which must happen before moving out of U-Boot, otherwise the controller will corrupt memory. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
2019-10-31dfu: add callback for flush and initiated operationPatrick Delaunay
Add weak callback to allow board specific behavior - flush - initiated This patch prepare usage of DFU back end for communication with STM32CubeProgrammer on stm32mp1 platform with stm32prog command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: add DFU virtual backendPatrick Delaunay
Add a virtual DFU backend to allow board specific read and write (for OTP update for example). Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
generated by cgit (git 2.34.1) at 2025-01-08 17:41:26 +0000