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2020-06-04sifive: fu540: add ddr driverPragnesh Patel
Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04misc: add driver for the SiFive otp controllerPragnesh Patel
Added a misc driver to handle OTP memory in SiFive SoCs. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-03Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- Toshiba spinand (Yoshio) - SPI/SPI Flash cleanup (Jagan) - Remove SH SPI (Jagan)
2020-06-03Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- H6 emac support - USB PHY H6 logic alignment
2020-06-03drivers: net: qe: deselect QE when DM_ETH is enabledMadalin Bucur
A compilation error appears when QE is compiled with DM_ETH enabled: drivers/qe/uec.c: In function 'init_phy': drivers/qe/uec.c:425:28: error: dereferencing pointer to incomplete type 'struct eth_device' uec = (uec_private_t *)dev->priv; ^~ drivers/qe/uec.c: In function 'uec_initialize': drivers/qe/uec.c:1357:43: error: invalid application of 'sizeof' to incomplete type 'struct eth_device' dev = (struct eth_device *)malloc(sizeof(struct eth_device)); ^~~~~~ The patch disables CONFIG_QE when CONFIG_DM_ETH is set. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-03drivers: net: e1000: with DM_ETH needs DM_PCI tooMadalin Bucur
Compilation error occur when DM_ETH is enabled without DM_PCI. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-02bootcount_ext: Add Ext4 build dependencyFrédéric Danis
This config option depends on EXT4 support. If Ext4 write capability is not selected, it generate write error messages and is unable to maintain boot counter. Signed-off-by: Frédéric Danis <frederic.danis@collabora.com>
2020-06-02kconfig: fix typo for OHCI host and add to DM listMarcin Juszkiewicz
Description said that OHCI is not supported for driver model while it was converted too. Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2020-06-02kconfig: mark SPL/TPL options for DM_KEYBOARDMarcin Juszkiewicz
All three options had the same description. Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2020-06-02usb: ohci: Add header file for ARCH_DMA_MINALIGNSimon Glass
This is defined in the asm/cache.h header file. Update this header file to include it so it gets the same value consistently across U-Boot. This fixes 'usb host' on omapl138_lcdk. Fixes: 90526e9fbac ("common: Drop net.h from common header") Reported-by: Adam Ford <aford173@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-06-02x86: spi: Rewrite logic for obtaining the SPI memory mapSimon Glass
At present this logic does not work on link and samus, since their SPI controller is not a PCI device, but a child of the PCH. Unfortunately, fixing this involves a lot of extra logic. Still, this was requested in the review of the fix-up patch, so here it is. Fixes: 92842147c31 ("spi: ich: Add support for get_mmap() method") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
2020-06-01net: sun8i_emac: Add support for the H6 variantSamuel Holland
The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01net: sun8i_emac: Use consistent clock bitfield definitionsSamuel Holland
While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01phy: sun4i-usb: Align H6 initialization logic with the kernelRoman Stratiienko
H6 SOC needs additional initialization of PHY registers. Corresponding changes can be found in the kernel patch [1]. Without this changes there is no enumeration of 'musb' gadget. [1] - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ae409cc7c3cdb9ac4a1dba3eae70efec3d6b6c79 Fixes: 35fa673e0e5f ("sunxi: phy: Add USB PHY support for Allwinner H6") Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01mtd: sf: Drop plat from sf_probeJagan Teki
dm_spi_slave_platdata used in sf_probe for printing plat->cs value and there is no relevant usage apart from this. We have enough debug messages available in SPI and SF areas so drop this plat get and associated bug statement. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01mtd: spi: Call sst_write in _write opsJagan Teki
Currently spi-nor code is assigning _write ops for SST and other flashes separately.  Just call the sst_write from generic write ops and return if SST flash found, this way it avoids the confusion of multiple write ops assignment during the scan and makes it more feasible for code readability. No functionality changes. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01sf: Drop spl_flash_get_sw_write_protJagan Teki
The get_sw_write_prot API is used to get the write-protected bits of flash by reading the status register and other wards it's API for reading register bits. 1) This kind of requirement can be achieved using existing flash operations and flash locking API calls instead of making a separate flash API. 2) Technically there is no real hardware user for this API to use in the source tree. 3) Having a flash operations API for simple register read bits also make difficult to extend the flash operations. 4) Instead of touching generic code, it is possible to have this functionality inside spinor operations in the form of flash hooks or fixups for associated flash chips. Considering all these points, this patch drops the get_sw_write_prot and associated code bases. Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01mtd: spi: Use CONFIG_IS_ENABLED to prevent ifdefJagan Teki
Use CONFIG_IS_ENABLED to prevent ifdef in sf_probe.c Cc: Simon Glass <sjg@chromium.org> Cc: Vignesh R <vigneshr@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Zap sh_spi driverJagan Teki
sh_spi driver is deprecated, no active updates and no board user, hence dropped the same. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Kconfig: Move MSCC_BB_SPI, FSL_QSPI into DM_SPIJagan Teki
- MSCC_BB_SPI - FSL_QSPI Both are fully dm-driven, let's move them into DM_SPI side definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Kconfig: Drop redundant CF_SPI definitionJagan Teki
CF_SPI kconfig option defined twice with DM_SPI and non DM_SPI. Drop the non DM_SPI side kconfig definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi Drop spi_init()Jagan Teki
spi_init doesn't exist anywhere in the code. Drop it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-31Merge tag 'u-boot-rockchip-20200531' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix mmc of path after syncfrom kernel dts; - Add dwc3 host support with DM for rk3399; - Add usb2phy and typec phy for rockchip platform; - Migrate board list doc to rockchip.rst; - Add rk3399 Pinebook Pro board support; - Update dram_init in board_init and add memory node in SPL;
2020-05-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini
- ehci-mx6, eth/r8152 bugfixes
2020-05-30Merge tag 'dm-pull-30may20' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-dm Patman changelog enhancements Sandbox SPI flash doc update
2020-05-29dm: core: Reorder include files in read.cStefan Roese
Including the assembler headers before including common.h etc leads to compilation errors upon MIPS64 based platforms using OF_LIVE. This patch reorders the include files to the "correct" oder. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-30driver: usb: drop legacy rockchip xhci driverFrank Wang
We have changed to use dwc3 generic driver for usb3.0 host, so the legacy Rockchip's xHCI driver is not needed, and drop it. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-30usb: dwc3: add make compatible for rockchip platformFrank Wang
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller in resetting to hold pipe power state in P2 before initializing the PHY. This commit fixed it and added device compatible for rockchip platform. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: ehci-mx6: Print error code on failureMarek Vasut
Print the error code if the regulator enable fails, otherwise the error message is rather useless and confusing. Signed-off-by: Marek Vasut <marex@denx.de>
2020-05-29usb: ehci-mx6: Handle fixed regulators correctlyMarek Vasut
The regulator-fixed would return -ENOSYS when enabled/disabled, because this operation is not supported, but this is not an error e.g. on systems where the VBUS cannot be controlled, so if this is the error code reported by the regulator core, consider it a success and continue. Signed-off-by: Marek Vasut <marex@denx.de>
2020-05-29eth/r8152: fix assigning the wrong endpointHayes Wang
Although I think it never occurs, the code doesn't make sense, because it may allow to assign an IN endpoint to ss->ep_out. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-05-29usb: dwc3: amend UTMI/UTMIW phy interface setupFrank Wang
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: dwc3: Enable AutoRetry feature in the controllerJagan Teki
By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: dwc3: Add disable u2mac linestate check quirkJagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: dwc3: add dis_u2_freeclk_exists_quirkFrank Wang
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29usb: dwc3: add dis_enblslpm_quirkFrank Wang
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29phy: rockchip: Add Rockchip USB TypeC PHY driverJagan Teki
Add USB TYPEC PHY driver for rockchip platform. Referenced from Linux TypeC PHY driver, currently supporting usb3-port and dp-port need to add it in the future. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29phy: rockchip: Add Rockchip USB2PHY driverJagan Teki
Add Rockchip USB2PHY driver with initial support. This will help to use it for EHCI controller in host mode, and USB 3.0 controller in otg mode. More functionality like charge, vbus detection will add it in future changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Enable/Disable TCPHY clocksJagan Teki
Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Set empty for TCPHY assigned-clocksJagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Enable/Disable the USB2PHY clkJagan Teki
Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29pci: Make Rockchip PCIe voltage regulators optionalMark Kettenis
The vpcie*-supply properties are optional and these are absent on boards like the ROCKPro64 and Firefly RK3399 where the voltage is supplied by always-on regulators that are already enabled upon boot. Make these regulators optional and properly check their presence before attempting to enable them. Makes PCIe work on un U-Boot on the boards mentioned above. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2020-05-29clk: rk3399: Fix eMMC get_clk reg offsetJagan Teki
Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-28misc: i2c_eeprom: implement different probe test eeprom offsetEugen Hristev
Because of this commit : 5ae84860b0 ("misc: i2c_eeprom: verify that the chip is functional at probe()") at probe time, each eeprom is tested for read at offset 0. The Atmel AT24MAC402 eeprom has different mapping. One i2c slave address is used for the lower 0x80 bytes and another i2c slave address is used for the upper 0x80 bytes. Because of this basically the i2c master sees 2 different slaves. We need the upper bytes because we read the unique MAC address from this EEPROM area. However this implies that our slave address will return error on reads from address 0x0 to 0x80. To solve this, implemented an offset field inside platform data that is by default 0 (as it is used now), but can be changed in the compatible table. The probe function will now read at this offset and use it, instead of blindly checking offset 0. This will fix the regression noticed on these EEPROMs since the commit abovementioned that introduces the probe failed issue. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-05-28i2c: observe scl_count in i2c_deblock_gpio_loop()Heinrich Schuchardt
When compiling with -Wtype-limits we see this error: drivers/i2c/i2c-uclass.c: In function ‘i2c_deblock_gpio_loop’: drivers/i2c/i2c-uclass.c:517:21: error: comparison of unsigned expression >= 0 is always true [-Werror=type-limits] 517 | while (scl_count-- >= 0) { | Don't loop forever. Fixes: 1f746a2c82b1 ("i2c: Make deblock delay and SCL clock configurable") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-28i2c: designware_i2c: Check if the device is poweredRaul E Rangel
If the device doesn't return a version that means the device is non-functional. The dw_i2c_regs had invalid offsets for the version field. I got the correct value from the DesignWare databook. It also matches what the Picasso PPR says. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested on chromebook_coral: Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-28i2c: designware_i2c: Tidy up use of NULL privSimon Glass
At present we still have pre-driver-model code in this driver and it makes things a bit confusing. In particular calc_bus_speed() is called with priv as NULL if not using driver model. This results in spk_cnt and comp_param1 being read from an invalid address if not using driver model. For comp_param1 this may not cause problems if reading from addresses close to 0 happens to be allowed, as high speed is only supported by DM code. But spk_cnt is subsequently used to calculate the bus periods and so this may cause problems (e.g. on spear600 board which has not been migrated yet). Add a new parameter regs parameter to calc_bus_speed() and add more comments to this function and to _dw_i2c_set_bus_speed(), which calls it. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-28mtd: spinand: toshiba: Support for new Kioxia Serial NANDYoshio Furuyama
Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-28mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)Yoshio Furuyama
The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-25phy: Fix possible NULL pointer deferenceVignesh Raghavendra
It is possible that users of generic_phy_*() APIs may pass a valid struct phy pointer but phy->dev can be NULL, leading to NULL pointer deference in phy_dev_ops(). So call generic_phy_valid() to verify that phy and phy->dev are both valid. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
generated by cgit (git 2.34.1) at 2024-12-25 13:23:31 +0000