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2020-06-29video: rockchip: fix HDMI 4K resolutionAnatolij Gustschin
3480 is not valid XRES, use 3840 as default. Fixes: 05c65a82c3c1 ("video: rockchip: Support 4K resolution for rk3399, HDMI") Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
2020-06-28Merge tag 'fixes-for-v2020.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix logo on mx6ul_14x14_evk with DM_VIDEO enabled - fix banner string overwriting the logo on small displays - fix splash warning when building for ARM64 - fix STM32 DSI driver to probe only on supported hardware - fix memory corruption with DSI panel drivers
2020-06-28rockchip: correctly set vop0 or vop1Patrick Wildt
The EDP_LCDC_SEL bit has to be set correctly to select vop0 or vop1, but so far we have set it in both conditions, which is not correct. Can someone verify this is the correct way round? vop1 -> set, vop0 -> clear? Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-28video: orisetech_otm8009a: fill characteristics of DSI data linkYannick Fertre
Fill characteristics of DSI data link to platform data instead of mipi device to avoid memory corruption. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: raydium_rm68200: fill characteristics of DSI data linkYannick Fertre
Fill characteristics of DSI data link to platform data instead of mipi device to avoid memory corruption. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: stm32: stm32_dsi: copy DSI fieldsYannick Fertre
Copy the DSI data link characteristics from panel platform data to mipi DSI device. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: check hardware version of DSIYannick Fertre
Check the hardware version of DSI. Versions 1.30 & 1.31 are only supported. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
2020-06-28video: vidconsole: avoid multiple lines overwrite logoYe Li
Fix the bug that multiple lines wraps to overwrite logo bmp display. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-28video: bmp: support 8bits BMP drawing on 24/32 bpp framebufferYe Li
Update video bmp code so that we can display 8 bits logo on 24 or 32 bpp framebuffer. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-27rockchip: clk: rk3188: change APLL to safe 600MHzAlexander Kochetkov
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver") changed ARM clock from 600MHz to 1600MHz. It made boot unstable due to the fact that PMIC at the start generates insufficient voltage for operation. See also: commit f4f57c58b589 ("rockchip: rk3188: Setup the armclk in spl"). Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-24Merge tag 'mmc-2020-6-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- Fix fsl_esdhc_imx tunning mask - Disable CMD CRC for normal tuning for fsl_esdhc_imx - Retry CM1 until emmc ready - Fix sdhci HISPD handling - Cache-aligned extcsd reading
2020-06-24mmc: sdhci: Fix HISPD bit handlingJagan Teki
SDHCI HISPD bits need to be configured based on desired mmc timings mode and some HISPD quirks. So, handle the HISPD bit based on the mmc computed selected mode(timing parameter) rather than fixed mmc card clock frequency. Linux handle the HISPD similar like this in below commit but no SDHCI_QUIRK_BROKEN_HISPD_MODE, commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling") This eventually fixed the mmc write issue observed in rk3399 sdhci controller. Bug log for refernece, => gpt write mmc 0 $partitions Writing GPT: mmc write failed ** Can't write to device 0 ** ** Can't write to device 0 ** error! Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Peng Fan <peng.fan@nxp.com> Peng Fan: added back "ctrl &= ~SDHCI_CTRL_HISPD;" per Jaehoon's suggestion Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> # roc-rk3399-pc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-24mmc: retry CMD1 in mmc_send_op_cond() until the eMMC is readyHaibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue CMD1 repeatedly in the idle state until the eMMC is ready even if mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC devices seems to enter the inactive mode after mmc_complete_op_cond() issued CMD0 when the eMMC device is busy. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-06-24mmc: fsl_esdhc_imx: disable the CMD CRC check for standard tuningHaibo Chen
In current code, we add 1ms dealy after each tuning command for standard tuning method. Adding this 1ms dealy is because USDHC default check the CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning IC logic do not wait for the tuning data sending out by the card, trigger the buffer read ready interrupt immediately, and step to next cycle. So when next time the new tuning command send out by USDHC, card may still not send out the tuning data of the upper command，then some eMMC cards may stuck, can't response to any command, block the whole tuning procedure. If do not check the CMD CRC for tuning, then do not has this issue. USDHC will wait for the tuning data of each tuning command and check them. If the tuning data pass the check, it also means the CMD line also okay for tuning. So this patch disable the CMD CRC check for tuning, save some time for the whole tuning procedure. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-06-23nvme: Invalidate dcache before submitting admin cmdJagan Teki
This patch try to avoids eviction of dirty lines during DMA transfer. The code right now execute the following step: - allocate the buffer - start a dma operation using the non-coherent dma buffer - invalidate cache lines associated with the buffer - read the buffer This can lead to reading back not valid information, because the cache controller could evict dirty cache lines belonging to the buffer *after* the DMA operation has started to fill the DRAM. In order to avoid this, a new invalidation is required *before* starting the DMA operation. The patch just adds an invalidation before submitting the DMA command. Example below shows the nvme disk scan result without the following patch => nvme scan nvme_get_info_from_identify: nn = 544502629, vwc = 100, sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105 So, invalidating the cache before submitting the admin command, fix the cpu read. Cc: André Przywara <andre.przywara@arm.com> Reported-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-23gpio: mxc_gpio: change gpio index for i.MX8Ye Li
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX platforms, so we have to adjust the index accordingly. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2020-06-22net: fec: Allow the PHY node to be retrievedFabio Estevam
As we move towards driver model, it is required to let the FEC driver know how to properly deal with an Ethernet PHY subnode in the device tree. For example: &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; phy: ethernet-phy@0 { reg = <0>; qca,clk-out-frequency = <125000000>; }; }; }; Currently the PHY node pointer is incorrectly associated with the Ethernel controller instead of the PHY node itself. This causes the PHY properties, such as "qca,clk-out-frequency" in the example above to not get parsed. Fix this problem by populating the phy_of_node node. Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Tom Rini <trini@konsulko.com>
2020-06-22phy: atheros: ar8035: Fix clock output calculationFabio Estevam
The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com>
2020-06-18firmware: PSCI: Fix PSCI support for OF live treesJon Hunter
When CONFIG_OF_LIVE is enabled, dev_of_offset() cannot be used and if used returns an invalid offset. This causes the call to fdt_stringlist_get() in the psci_probe() to fail to read the 'method' property from the PSCI node for the device and hence prevents PSCI from working. Fix this by using the ofnode_read_string() API instead of the fdt_stringlist_get() because this will handle reading the property both when CONFIG_OF_LIVE is enabled or disabled. Due to the above problem and since commit 81ea00838c68 ("efi_loader: PSCI reset and shutdown") was added, the EFI system reset has been broken for Tegra210 and Tegra196 platforms. This also fixes the EFI system reset for these Tegra platforms. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-06-15regulator: fix: enable gpio when requestedMark Kettenis
The fix in commit b7adcdd073c0 has the side-effect that the regulator will be disabled when requesting the relevant gpio in regulator_common_ofdata_to_platdata() and enabled in regulator_pre_probe() when the regulator was already enabled. This leads to a short interruption in the 3.3V power to the PCIe slot on the firefly-rk3399 which makes an ADATA SX8000NP NVMe SSD unhappy. Fix this by setting the GPIOD_IS_OUT_ACTIVE flag again when the 'regulator-boot-on' property is set, but check for this property explicitly instead of relying on the "boot_on" member of the uclass platdata. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-15Merge tag 'mmc-2020-6-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- fsl_esdhc sdr104 and hs200 fix and error path fix - fsl_esdhc workaround 3.3v io issue - ca_dw_mmc cleanup - presidio-asic emmc DT update.
2020-06-15mmc: fsl_esdhc: Gracefully fail on unsupported voltage switchMarek Vasut
Unsupported voltage on voltage switch is not an error, do not print error message in such a case. This happens e.g. if the eMMC is already in 1V8 mode or when testing 1V2 mode operation on systems which only do 3V3/1V8 switching. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-06-15mmc: fsl_esdhc: Fix SDR104 and HS200 supportMarek Vasut
The 3V3/1V8 switching could never have worked on any of the iMXes ever since 51313b49f2 ("mmc: fsl_esdhc: support SDR104 and HS200"), because that commit uses priv->vqmmc_dev when switching voltages on mode switch, while local vqmmc_dev in probe to store the regulator pointer. Those are two different variables with the same name. So the priv->vqmmc_dev was always NULL and thus voltage switch between modes never really suceeded. Fix this by assigning priv->vqmmc_dev with value of the vqmmc_dev in probe. Fixes: 51313b49f2 ("mmc: fsl_esdhc: support SDR104 and HS200") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-06-15mmc: ca_dw_mmc: Misc cleanup of driverArthur Li
- Rename DT compatible name - Remove uneccessary if-statement to support 8-bit buswidth - Remove redundant error msg - Use symbolic constants in switch statement Signed-off-by: Arthur Li <arthur.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Peng Fan <peng.fan@nxp.com> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Tom Rini <trini@konsulko.com>
2020-06-15mmc: fsl_esdhc: workaround for hardware 3.3v IO reliability issueYangbo Lu
When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface runs, the more damage accumulates. This issue now is found on LX2160A eSDHC1 for only SD card. The hardware workaround is recommended to use an on-board level shifter that is 1.8v on SoC side and 3.3v on SD card side. For boards without hardware workaround, this option could be enabled, ensuring 1.8v IO voltage and disabling eSDHC if no card. This option assumes no hotplug, and u-boot has to make all the way to to linux to use 1.8v UHS-I speed mode if has card. If you do not want the workaround for better user experience, of course you can choose to not select it running eSDHC in unsafe mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2020-06-15mmc: fsl_esdhc: read register once for card inserted statusYangbo Lu
No need to poll register for card inserted status. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2020-06-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini
- eth/r8152: update the firmware
2020-06-14eth/r8152: update the firmwareHayes Wang
Update the firmware to improve compatibility for none-intel USB host controller. The more information is as following. The device has auto-installed driver feature - via switch CD-ROM/NIC mode. But in some corner cases, it would switch to CD-ROM unexpected. This issue results in Lan Function Disabled. While USB PHY transits to P3 from P0 due to the absent of transmitter control, it would issues undefined signal to its link partner. Some Down Stream Port misidentify the undefined signal as wakeup signal. So the link state will not keep in suspend even the system is idle. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-06-11spi: davinci: Drop non-dm codeJagan Teki
Now all boards which are using davinci SPI driver have moved to SPL_DM so drop the unneeded non-dm code. Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
2020-06-11spi: atmel: Drop atmel_spi.hJagan Teki
atmel_spi.h has register offsets, and atmel_spi_slave structure, move it into .c file for better readability and drop atmel_spi.h Cc: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11spi: atmel: Remove nondm codeJagan Teki
atmel spi driver now accessible only when DM_SPI enabled. So, remove nondm code. Cc: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11spi: atmel: Drop CONFIG_SYS_SPI_WRITE_TOUTJagan Teki
Drop CONFIG_SYS_SPI_WRITE_TOUT there is no code usage. Cc: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11spi: fsl_dspi: Drop nondm codeJagan Teki
Drop the nondm code from fsl_dspi.c since there is no board or any other code using for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11spi: Zap SOFT_SPI (non-dm)Jagan Teki
- Deadline for DM migration already passed by months. - Sent couple of zap patches and - No response on dm conversation hence removed the driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-06-11spi: mxs: Code cleanupJagan Teki
Order the macros, private structures and simple functions in a proper way to have more code readability. No functionality changed. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11spi: mxs: Drop nondm codeJagan Teki
Deadline for DM migration already passed by months and no response on full dm conversation hence removed the nondm code. Note: Look like there is no user for nondm code for this driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-09Merge tag 'u-boot-imx-20200609' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.07 ----------------- - mx53: mx53menlo Convert to DM_ETH, fix fail boot - imx8mp_evk: fix boot issue - MX6, display5: fix environment - drop warnings (watchdog) for i.MX8mm i.mx8mp - enable bootaux for i.MX8M Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
2020-06-08Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug fixes - Add TBI PHY access through MII - DDR: Rework errata workaround for A008109, A008378, 009942
2020-06-08power: pmic: Add SPL Kconfig entry for PFUZE100Marek Vasut
Add Kconfig entry for the PFUZE PMIC, SPL variant. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-06-05virtio: VIRTIO_RNG depends on DM_RNGHeinrich Schuchardt
Add the missing Kconfig dependency and let VIRTIO_RNG default to yes. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04serial: Add missing Kconfig dependencies for debug consolesMichal Simek
Debug console is the part of serial driver in the same file. It means to be able to enable debug console you also need to enable driver itself. That's why add all dependecies and list only debug consoles which are enabled based on driver selection to avoid compilation error when user asks for certain debug console but driver is not enable for it. Error: aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `putc': /home/monstr/data/disk/u-boot/common/console.c:513: undefined reference to `printch' aarch64-linux-gnu-ld.bfd: common/built-in.o: in function `puts': /home/monstr/data/disk/u-boot/common/console.c:563: undefined reference to `printch' Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Fix ns16550 dependency, add ZYNQ_SERIAL, change S5P] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-04serial: Convert ARM_DCC to KconfigTom Rini
The symbol "CONFIG_ARM_DCC" is used to control building drivers/serial/arm_dcc.c. Provide a simple Kconfig entry for this. Cc: Luca Ceresoli <luca@lucaceresoli.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Tom McLeod <tom.mcleod@opalkelly.com> Cc: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2020-06-04ddr: Rework errata A008109, A008378, 009942 workaroundJaiprakash Singh
Move errata A008109, A008378, 009942 workaround implementation from compute_fsl_memctl_config_regs() to fsl_ddr_set_memctl_regs() and add register write after each workaround implementation. Signed-off-by: Jaiprakash Singh <Jaiprakash.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04ddr: fsl: Impl. Erratum A008109Joakim Tjernlund
Impl. erratum as descibed in errata doc. Enable A008109 for T1040 and T1024 Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04net: tsec: Access TBI PHY through the corresponding MIIHou Zhiqiang
When an eTSEC is configured to use TBI, configuration of the TBI is done through the MIIM registers for that eTSEC. For example, if a TBI interface is required on eTSEC2, then the MIIM registers starting at offset 0x2_5520 are used to configure it. Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04net: tsec: Access eTSEC registers using virtual addressHou Zhiqiang
The current code accesses eTSEC registers using physical address directly, it's not correct, though no problem on current platforms. It won't work on platforms, which does not support 1:1 virtual-physical address map. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04net: tsec: fsl_mdio: add DM MDIO supportMadalin Bucur
Allow the MDIO devices to be probed based on the device tree. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel
U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel
Release ddr clock reset once clock is initialized Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel
Added clock enable and disable functions in prci ops Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2024-12-25 00:53:40 +0000