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2014-09-25mtd: nand: Fix length bug in ioread16_rep() and iowrite16_rep()Stefan Roese
The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific and have been introduced with the Linux MTD v3.14 sync. While introducing these functions, the length for the loop has been miscalculated. The ">> 1" is already present in the caller. So lets remove it in the function. Tested on omap3_ha. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Heiko Schocher <hs@denx.de>
2014-09-25mtd: nand: am335x: Fix 'bit-flip' errors in SPLRostislav Lisovy
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html The issue was partially fixed with the cc81a5291910d7a.git however this has to be done to fix the SPL. The original author of the code is Belisko Marek <marek.belisko@gmail.com> Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-25driver/ddr/fsl: Fix DDR4 driverYork Sun
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25driver/ddr/fsl: Fix tXP and tCKEYork Sun
The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25driver/ddr: Restruct driver to allow standalone memory spaceYork Sun
U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha
Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-24kbuild: refactor some makefilesMasahiro Yamada
[1] Move driver/core/, driver/input/ and drivers/input/ entries from the top Makefile to drivers/Makefile [2] Remove the conditional by CONFIG_DM in drivers/core/Makefile because the whole drivers/core directory is already selected by CONFIG_DM in the upper level [3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile [4] Simplify common/Makefile - both CONFIG_DDR_SPD and CONFIG_SPD_EEPROM are boolean macros so they can directly select objects Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-24cosmetic: replace MIN, MAX with min, maxMasahiro Yamada
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-24kconfig: add blank Kconfig filesMasahiro Yamada
This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-09-24e1000: fix no nvm buildMarcel Ziswiler
Fix the following build error in case CONFIG_E1000_NO_NVM is enabled: CC drivers/net/e1000.o drivers/net/e1000.c: In function ‘e1000_initialize’: drivers/net/e1000.c:5365:5: error: ‘struct e1000_hw’ has no member named ‘eeprom_semaphore_present’ make[1]: *** [drivers/net/e1000.o] Error 1 make: *** [drivers/net] Error 2 Acked-by: Marek Vasut <marex@denx.de>
2014-09-24usb/gadget: fastboot: minor cleanupSteve Rae
- update static function - additional debugging statements - update "fastboot command" information - add missing include file - update spelling Signed-off-by: Steve Rae <srae@broadcom.com>
2014-09-24usb/gadget: fastboot: add support for flash commandSteve Rae
- implement 'fastboot flash' for eMMC devices Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Marek Vasut <marex@denx.de>
2014-09-24board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-09-24spi: kirkwood_spi.c: cosmetic: Fix minor coding style issuesStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24spi: kirkwood_spi.c: Make global variable staticStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24spi: kirkwood_spi.c: Some fixes and cleanupStefan Roese
This patch introduces the clrsetbits_le32() accessor functions in the kirkwood SPI driver. Note that it also includes a fix: - writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); + writel(KWSPI_SMEMRDY, &spireg->ctrl); Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead 0xfffffffe is written into this control register. This is the main reason to use the clrsetbits() functions now. As they make clearing bits much less error prone. Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and spi_cs_deactivate() any more. Its the wrong macro but has the same value as the correct one (KWSPI_CSN_ACT). This is in preparation for use of this driver on the Marvell Armada XP platform as well. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24sf: Add M25PX64 SPI NOR flash IDStefan Roese
Add ID for this Numonix / STMicro chip. Tested on Marvell DB-78460-BP board. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*Nikita Kiryanov
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in SPL. These #defines do not allow the user to select SPI mode for the SPI flash (there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in spi_spl_load.c), and duplicate information already provided by CONFIG_SF_DEFAULT_* #defines. Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead. Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Bo Shen <voice.shen@atmel.com> Cc: Hannes Petermaier <hannes.petermaier@br-automation.com> Cc: Michal Simek <monstr@monstr.eu> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24spi: mxc: fix sf probe when using mxc_spiNikita Kiryanov
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high across multiple transactions. This is set up by embedding the GPIO information in the CS value: cs = (cs | gpio << 8) This merge of cs and gpio data into one value breaks the sf probe command: if the use of gpio is required, invoking "sf probe <cs>" will not work, because the CS argument doesn't have the GPIO information in it. Instead, the user must use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must type "sf probe 15872". This is inconsistent with the description of the sf probe command, and forces the user to be aware of implementaiton details. Fix this by introducing a new board function: board_spi_cs_gpio(), which will accept a naked CS value, and provide the driver with the relevant GPIO, if one is necessary. Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Eric Benard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24mtd: spi: add support for M25PE16 and M25PX16Nikita Kiryanov
Add support for M25PE16 and M25PX16 Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-23dm: avoid dev->req_seq overflowRobert Baldyga
Since dev->req_seq value is initialized from "reg" property of fdt node, there is posibility, that address value contained in fdt is greater than INT_MAX, and then value in dev->req_seq is negative which led to probe() fail. This patch fix this problem by ensuring that req_seq is positive, unless it's one of errno codes. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-09-23dm: serial: Don't require device tree to configure a consoleSimon Glass
Allow serial_find_console_or_panic() to work without a device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23dm: core: Allow device_bind() to used without CONFIG_OF_CONTROLSimon Glass
The sequence number support in driver model requires device tree control. It should be skipped if CONFIG_OF_CONTROL is not defined, and should not require functions from fdtdec. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23sf: Add an empty entry to the parameter listSimon Glass
The list is supposed to be terminated with a NULL name, but is not. If a board probes a chip which does not appear in the table, U-Boot will crash (at least on sandbox). Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-19mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECCBoris BREZILLON
Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19USB: ehci-atmel: use pcr to enable or disable clockBo Shen
If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19USB: ohci-at91: use pcr to enable or disable clockBo Shen
If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc registerWu, Josh
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-17Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-09-16net: usb: Add SMSC copyright to smsc95xx driverSimon Glass
This driver was upstreamed without an SMSC copyright, even thought it seems that SMSC was the original author. See the kernel version for a code comparison: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190 It's not clear who actually moved this code, or whether the kernel was the original source, or somewhere else, but it probably should still have the SMSC copyright. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-16mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREADmaxin.john@enea.com
This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-09-16mtd: nand: davinci_nand: update write_page function for keystone RBLKhoronzhuk, Ivan
After mtd was synced with Linux 3.14 (ff94bc40af3481d47546595ba73c136de6af6929) the number of parameters for write_page function of nand_chip was changed. The additional two var were needed for subpage write. As keystone has no supbage write they are not needed. So correct only function definition by upgrading it's parameter list. That helps to get ritd of compilation warning. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-16kbuild: force to define __UBOOT__ in all the C sourcesMasahiro Yamada
U-Boot has imported various source files from other projects, mostly Linux. Something like #ifdef __UBOOT__ [ modification for U-Boot ] #else [ original code ] #endif is an often used strategy for clarification of adjusted parts, that is, easier re-sync in future. Instead of defining __UBOOT__ in each source file, passing it from the top Makefile would be easier. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
2014-09-16rtl8169: Defer network packet processingThierry Reding
When network protocol errors occur (such as a file not being found on a TFTP server), the processing done by the NetReceive() function will end up calling the driver's .halt() implementation. However, after that the device no longer has access to the memory buffers and will cause errors such as this in the rtl_recv() function when trying to hand descriptors back to the device: pci_hose_bus_to_phys: invalid physical address This can be fixed by deferring processing of network packets until the descriptors have been handed back. That way rtl_halt() tearing down network buffers is not going to prevent access to the buffers. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-09-15openrisc: Fix a few type cast related warningsVasili Galka
Use size_t type for positive offsets instead of the loff_t type. The later is defined as long long, which is larger than the pointer type on OpenRISC architecture and therefore the following warning was generated: "warning: cast to pointer from integer of different size" Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-09-13Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini
2014-09-12Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-09-10dm: tegra: Enable driver model for serialSimon Glass
Use driver model for serial ports. Since Tegra now uses driver model for serial, adjust the definition of V_NS16550_CLK so that it is clear that this is only used for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10dm: serial: Add driver model support for ns16550Simon Glass
Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10dm: serial: Collect common baud rate code in ns16550Simon Glass
The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10dm: serial: Move baud rate calculation to ns16550.cSimon Glass
Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10sandbox: serial: Support a coloured consoleSimon Glass
The current sandbox serial driver is a pretty trivial example and does not have the featues that might be needed for other board serial drivers. To help provide a better example, add a text colour property to the device tree for sandbox. This uses platform data, a device tree node, driver private data and a remove() method. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10sandbox: Convert serial driver to use driver modelSimon Glass
Adjust the sandbox serial driver to use the new driver model uclass. The driver works much as before, but within the new framework. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10dm: Add a uclass for serial devicesSimon Glass
Serial devices support simple byte input/output and a few operations to find out whether data is available. Add a basic uclass for serial devices to be used by drivers that are converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10dm: Adjust lists_bind_fdt() to return the bound deviceSimon Glass
Allow the caller to find out the device that was bound in response to this call. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10serial: Set up the 'priv' pointer when creating a serial deviceSimon Glass
The stdio_dev structure has a private pointer for its creator, but it is not set up by the serial system. Set it to point to the serial device so that it can be found by code called by stdio. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10tegra: Convert tegra GPIO driver to use driver modelSimon Glass
This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-09pcie_imx: Add mx6solox supportFabio Estevam
Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-09arm: vf610: lpuart: disable FIFO on initializatonStefan Agner
UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09arm: vf610: lpuart: fix status register handlingStefan Agner
The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>