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2017-05-10rockchip: video: Add mipi driver support for rockchip socEric Gao
Add basic driver for mipi display on rockchip soc platform. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10power: rk808: rename to rk8xxJacob Chen
Since this driver can be used for rk8xx series pmic, let's rename rk808 to rk8xx, to make it clear. Configs parts are done by sed -i "s/RK808/RK8XX/g" `grep RK808 -lr ./` Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
2017-05-10power: regulator: rk808: add rk818 supportJacob Chen
Add support for the rk818 regulator. The regulator module consists of 4 DCDCs, 9 LDOs, 1 switch and 1 BOOST converter which is used to power OTG and HDMI5V. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10power: regulator: rk808: replace vsel_bits with vsel_maskJacob Chen
Using mask is more flexible than bits. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10power: pmic: rk808: add RK818 supportJacob Chen
The RK818 chip is a Power Management IC (PMIC) for multimedia and handheld devices. For boards use rk818, the input current should be set in the early stage, before ddr initialization. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
2017-05-10power: pmic: append rk818 regs to rk808Jacob Chen
Both RK808 and RK818 chips are using a similar register map, so we can reuse them. I have also add reg prefix to exist registers, to keep them same style. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10i2c_eeprom: add read and write functionsJonas Karlman
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add support for the HDMI I2C pinsPhilipp Tomsich
To add HDMI support for the RK3399, this commit provides the needed pinctrl functionality to configure the HDMI I2C pins (used for reading the screen's EDID). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: allow requests for HDMI clocksPhilipp Tomsich
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF, which are clock gates in the HDMI output path for the RK3399. As these are enabled by default (i.e. after reset), we don't implement any logic to actively open/close these clock gates and simply assume that their reset-default has not been changed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NSPhilipp Tomsich
The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS. To allow us to add a efuse-driver (and more importantly, to allow probes of such a driver to succeed), we need need to accept requests for PCLK_EFUSE1024NS and return a non-error result. As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't implement any logic to manage this clock gate and simply assume that the reset-default has not been changed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: sandbox: pwm: add test for pwm_set_invert()Kever Yang
Add test case for new interface set_invert(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fix typo in subject and build error in sandbox_pwm_set_invert(): Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pwm: implement pwm_set_invert()Kever Yang
Rockchip pwm need to init polarity, implement pwm_set_invert() to do it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10power: regulator: pwm: support pwm polarity settingKever Yang
The latest kernel PWM drivers enable the polarity settings. When system run from U-Boot to kerenl, if there are differences in polarity set or duty cycle, the PMW will re-init: close -> set polarity and duty cycle -> enable the PWM. The power supply controled by pwm regulator may have voltage shaking, which lead to the system not stable. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: mmc: handle deprecation of 'clock-freq-min-max'Philipp Tomsich
The 'clock-freq-min-max' property was deprecated in the upstream (i.e. Linux) DTS bindings in favor of the 'max-frequency' property. With the latest RK3399 DTSI does no longer include the deprecated property and the rockchip_dw_mmc driver requiring it to be present, the driver doesn't bind to the node in the RK3399 DTSI any longer (thus breaking access to the SD card on the RK3399-Q7 board). To fix this, we implement a similar logic as in the Linux driver: if the deprecated property is present, we issue a warning (if DEBUG is enabled); if it is missing, we require 'max-frequency' to be set and use it to create a min/max value-pair. See https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b for the deprecation/matching change in Linux. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTSPhilipp Tomsich
The clocking of the designware MMC controller in the upstream (i.e. Linux) RK3399 has changed/does not match what the current DTS in U-Boot uses: the first clock entry now is HCLK_SDMMC instead of SCLK_SDMMC. With the simple clock driver used for the RK3399, this needs a change in the selector understood by the various case statements in the driver to ensure that the driver still loads successfully. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add gmac io strength supportKever Yang
GMAC controller need to init the tx io driver strength to 13mA, just like the description in dts pinctrl node, or else the controller may only work in 100MHz Mode, and fail to work at 1000MHz mode. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: spi: enable support for the rk_spi driver for the RK3399Jakob Unterwurzacher
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware block found in the RK3399. This has been confirmed both with SPI NOR flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5. This change adds the 'rockchip,rk3399-spi' string to its compatible list to allow reuse of the existing driver. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: pinctrl: rk3399: add support for the SPI5 controllerPhilipp Tomsich
This commit adds support for the pin-configuration of the SPI5 controller of the RK3399 through the following changes: * grf_rk3399.h: adds definition for configuring the SPI5 pins in the GPIO2C group * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3 through SPI5 to the appropriate pin-config function; implements the pin-configuration for PERIPH_ID_SPI5 using the GPIO2C group X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate settingPhilipp Tomsich
The baudrate in rkspi was calculated by using an integer division (which implicitly discarded any fractional result), then rounding to an even number and finally clamping to 0xfffe using a bitwise AND operator. This introduced two issues: 1) for very small baudrates (overflowing the 0xfffe range), the bitwise-AND generates rather random-looking (wildly varying) actual output bitrates 2) for higher baudrates, the calculation tends to 'err towards a higher baudrate' with the actual error increasing as the dividers become very small. E.g., with a 99MHz input clock, a request for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use (which amounts to a 23.75% error)... for a 34 MBit request this would be an actual outbout of 49.5 Mbit (i.e. a 45% error). This change rewrites the divider selection (i.e. baudrate calculation) by making sure that a) for the normal case: the largest representable baudrate below the requested rate will be chosen; b) for the denormal case (i.e. when the divider can no longer be represented), the lowest representable baudrate is chosen. Even though the denormal case (b) may be of little concern in real world applications (even with a 198MHz input clock, this will only happen at below approx. 3kHz/3kBit), our board-verification team kept complaining. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-05-10rockchip: spi: rk_spi: dynamically select an module input ratePhilipp Tomsich
The original clock/bitrate selection code for the rk_spi driver was a bit limited, as it always selected a 99MHz input clock rate (which would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL if a bitrate higher than 48MHz was requested. To give us better control over the bitrate (i.e. add more operating points, especially at "higher" bitrate---such as above 9MBit/s), we try to choose 4x the maximum frequency (clamped to 50MBit) from the DTS instead of 99MHz... for most use-cases this will yield a frequency of 198MHz, but is flexible to go beyond this in future configurations. This also rewrites the check to allow frequencies of up to half the SPI module rate as bitrates and then clamps to whatever the DTS allows as a maximum (board-specific) frequency and does away with the -EINVAL when trying to select a bitrate (for cases that exceeded the hard limit) and instead consistently clamps to the lower of the hard limit, the soft limit for the SPI bus (from the DTS) or the soft limit for the SPI slave device. This replaces "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399" "rockchip: spi: rk_spi: improve clocking code for the RK3399" from earlier versions of this series. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10rockchip: clk: rk3399: fix off-by one during rate calculation in ↵Philipp Tomsich
i2c/spi_set_rate For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events: 1. calculates 'src_div := src_freq / target_freq' 2. stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1) 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)') This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return. To fix, we have two options: * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read * we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5Philipp Tomsich
This change adds support for configuring the module clocks for SPI1 and SPI5 from the 594MHz GPLL. Note that the driver (rk_spi.c) always sets this to 99MHz, but the implemented functionality is more general and will also support different clock configurations. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: video: Makefile: Modify Makefile for rockchip video drivereric.gao@rock-chips.com
Modify Makefile for rockchip video driver according to Kconfig, so that source code will not be compiled if not needed. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: video: Kconfig: Add Kconfig for rockchip video drivereric.gao@rock-chips.com
1. add Kconfig for rockchip video driver, so that video port can be selected as needed. 2. move VIDEO_ROCKCHIP option to new Kconfig for concision. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Drop indenting in Kconfig: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMCXu Ziyuan
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIOXu Ziyuan
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIOXu Ziyuan
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIOXu Ziyuan
The genunie bus clock is sclk_x for eMMC/SDIO, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10mmc: dw_mmc: rockchip: select proper card clockXu Ziyuan
As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is used for communication between host and card devices. The real bus clock is ciu, so let's rectify it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: power: domain: add BCM6328 power domain driverÁlvaro Fernández Rojas
This allows controlling MISC IDDQ register on BCM6328 SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-05-10dm: reset: add BCM6345 reset driverÁlvaro Fernández Rojas
This is a simplified version of linux/arch/mips/bcm63xx/reset.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: clk: add BCM6345 clock driverÁlvaro Fernández Rojas
This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: led: add BCM6358 led driverÁlvaro Fernández Rojas
This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: led: add BCM6328 led driverÁlvaro Fernández Rojas
This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c, simplified to remove HW leds and blink fallbacks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10dm: gpio: add BCM6345 gpio driverÁlvaro Fernández Rojas
This driver is based on linux/arch/mips/bcm63xx/gpio.c, simplified to allow defining one or two independent banks for each Broadcom SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10ram: add RAM driver for Broadcom MIPS SoCsÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10cpu: add CPU driver for Broadcom MIPS SoCsÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10serial: add serial driver for BCM6345Álvaro Fernández Rojas
It is based on linux/drivers/tty/serial/bcm63xx_uart.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10sysreset: add syscon-reboot driverÁlvaro Fernández Rojas
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c, which provides a generic driver for platforms that only require writing a mask to a regmap offset. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09power: twl4030: Move CONFIG_TWL4030_POWER to KconfigAdam Ford
As requested, I added the CONFIG_TWL4030_POWER to Kconfig and made it the implied default when selecting OMAP34XX as a platform. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09power: twl4030: Add CONFIG_CMD_POWEROFF supportAdam Ford
With the addition of twl4030_power_off(), let's allow the 'poweroff' command to run this function when CONFIG_CMD_POWEROFF is enabled. Tested on a DM3730 with twl4030 PMIC. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-05-09ARM: OMAP: I2C: Support New read, write and probe functions for OMAP3Adam Ford
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 (4430/60/70), OMAP5 (5430) and AM335X (3359) were added in 960187ffa125( "ARM: OMAP: I2C: New read, write and probe functions") but not tested on OMAP3. This patch will allow the updated drivers using device tree and DM_I2C to operate on OMAP3. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-09omap_hsmmc: update struct hsmmc to accommodate omap3 from DTAdam Ford
This patch changes the way DM_MMC calculates offset to the base register of MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3. This patch will now add in the offset to the base address based on the .compatible flags. Signed-off-by: Adam Ford <aford173@gmail.com> V2: Remove ifdef completely and reference offset from the omap_hsmmc_ids table. V1: Change ifdef to ignore OMAP3 Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09bcm2835_wdt: support for the BCM2835/2836 watchdogPaolo Pisati
Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
2017-05-09dm: video: arm: rpi: Convert to use driver model for videoSimon Glass
Adjust the video driver to work with driver model and move over existing baords. There is no need to keep the old code. We can also drop setting of CONFIG_FB_ADDR since driver model doesn't have this problem. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2017-05-09video: arm: rpi: Move the video settings out of the driverSimon Glass
Add a function to set the video parameters to the msg handler and remove it from the video driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2017-05-09video: arm: rpi: Move the video query out of the driverSimon Glass
Add a function to get the video size to the msg handler and remove it from the video driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2017-05-09dm: mmc: rpi: Convert Raspberry Pi to driver model for MMCSimon Glass
Convert the bcm2835 SDHCI driver over to support CONFIG_DM_MMC and move all boards over. There is no need to keep the old code since there are no other users. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-09net: smsc95xx: Correct free_pkt() implementationSimon Glass
On further review this returns the wrong packet length from the driver. It may not be noticed since protocols will take care of it. Fix it by subtracting the header length from the packet length returned. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-09Merge git://git.denx.de/u-boot-dmTom Rini