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2019-08-27stm32mp1: clk: remove debug tracesPatrick Delaunay
Remove many debug trace. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: add pattern parameter in infinite write testPatrick Delaunay
Add pattern for infinite test_read and test_write, that allow to change the pattern to test without recompilation; default pattern is 0xA5A5AA55. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: reload watchdog during ddr testPatrick Delaunay
Avoid watchdog during infinite DDR test. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: update loop management in infinite testPatrick Delaunay
Reduce verbosity of the infinite tests to avoid CubeMX issue. test and display loop by 1024*1024 accesses: read or write. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27stm32mp1: ram: fix address issue in 2 testsPatrick Delaunay
If user choose to test memory size is 1GByte (0x40000000), memory address would overflow in test "Random" and test "FrequencySelectivePattern". Thus the system would hangs up when running DDR test. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Bossen WU <bossen.wu@st.com>
2019-08-27stm32mp1: ram: cosmetic: remove unused prototypePatrick Delaunay
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27serial: stm32: add Framing error supportPatrick Delaunay
Add management of Bit 1 of USART_ISR = FE: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register (for stm32 after f4). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27mmc: stm32_sdmmc2: reload watchdogChristophe Kerello
This patch solves a watchdog reset issue during mmc erase command. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27pinctrl: stmfx: update pinconf settingsPatrick Delaunay
Alignment with kernel driver. According to the following tab (coming from STMFX datasheet), updates have to done in stmfx_pinctrl_conf_set function: -"type" has to be set when "bias" is configured as "pull-up or pull-down" -PIN_CONFIG_DRIVE_PUSH_PULL should only be used when gpio is configured as output. There is so no need to check direction. DIR | TYPE | PUPD | MFX GPIO configuration ----|------|------|--------------------------------------------------- 1 | 1 | 1 | OUTPUT open drain with internal pull-up resistor ----|------|------|--------------------------------------------------- 1 | 1 | 0 | OUTPUT open drain with internal pull-down resistor ----|------|------|--------------------------------------------------- 1 | 0 | 0/1 | OUTPUT push pull no pull ----|------|------|--------------------------------------------------- 0 | 1 | 1 | INPUT with internal pull-up resistor ----|------|------|--------------------------------------------------- 0 | 1 | 0 | INPUT with internal pull-down resistor ----|------|------|--------------------------------------------------- 0 | 0 | 1 | INPUT floating ----|------|------|--------------------------------------------------- 0 | 0 | 0 | analog (GPIO not used, default setting) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27pinctrl: pinctrl_stm32: cosmetic: Reorder include filesPatrice Chotard
Reorder include files Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27rtc: stm32: manage 2 digit limitation on yearPatrick Delaunay
STM32 RTC manages only 2 digits for YEAR (Year tens and units in BCD format in RTC_DR register). With this patch, RTC driver assumes that tm->tm_years is between 2000 and 2099; tm->tm_year - 2000 have only 2 digit (0 > and <= 99). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-27mmc: sti_sdhci: Fix sdhci_setup_cfg() call.Patrice Chotard
host->mmc, host->mmc->dev and host->mmc->priv must be set before calling sdhci_setup_cfg() to avoid hang during mmc initialization. Thanks to commit 3d296365e4e8 ("mmc: sdhci: Add support for sdhci-caps-mask") which put this issue into evidence. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-27mmc: stm32_sdmmc2: Increase SDMMC_BUSYD0END_TIMEOUT_USPatrice Chotard
Increase SDMMC_BUSYD0END_TIMEOUT_US from 1s to 2s to avoid timeout error during blocks erase on some sdcard Issue seen on Kingston 16GB : Device: STM32 SDMMC2 Manufacturer ID: 27 OEM: 5048 Name: SD16G Bus Speed: 50000000 Mode: SD High Speed (50MHz) card capabilities: widths [4, 1] modes [SD Legacy, SD High Speed (50MHz)] host capabilities: widths [4, 1] modes [MMC legacy, SD Legacy, MMC High Speed (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz)] Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.5 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes Issue reproduced with following command: STM32MP> mmc erase 0 100000 MMC erase: dev # 0, block # 0, count 1048576 ... mmc erase failed 16384 blocks erased: ERROR By setting SDMMC_BUSYD0END_TIMEOUT_US at 2 seconds and by adding time measurement in stm32_sdmmc2_end_cmd() as shown below: +start = get_timer(0); /* Polling status register */ ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, SDMMC_BUSYD0END_TIMEOUT_US); +printf("time = %ld ms\n", get_timer(start)); We get the following trace: STM32MP> mmc erase 0 100000 MMC erase: dev # 0, block # 0, count 1048576 ... time = 17 ms time = 1 ms time = 1025 ms time = 54 ms time = 56 ms time = 1021 ms time = 57 ms time = 56 ms time = 1020 ms time = 53 ms time = 57 ms time = 1021 ms time = 53 ms time = 57 ms time = 1313 ms time = 54 ms time = 56 ms time = 1026 ms time = 54 ms time = 56 ms time = 1036 ms time = 54 ms time = 56 ms time = 1028 ms time = 53 ms time = 56 ms time = 1027 ms time = 54 ms time = 56 ms time = 1024 ms time = 54 ms time = 56 ms time = 1020 ms time = 54 ms time = 57 ms time = 1023 ms time = 54 ms time = 56 ms time = 1033 ms time = 53 ms time = 57 ms .... time = 53 ms time = 57 ms time = 1021 ms time = 56 ms time = 56 ms time = 1026 ms time = 54 ms time = 56 ms 1048576 blocks erased: OK We see that 1 second timeout is not enough, we also see one measurement up to 1313 ms. Set the timeout to 2 second to keep a security margin. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-08-26Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-26nvme: Fix PRP Offset InvalidAaron Williams
When large writes take place I saw a Samsung EVO 970+ return a status value of 0x13, PRP Offset Invalid. I tracked this down to the improper handling of PRP entries. The blocks the PRP entries are placed in cannot cross a page boundary and thus should be allocated on page boundaries. This is how the Linux kernel driver works. With this patch, the PRP pool is allocated on a page boundary and other than the very first allocation, the pool size is a multiple of the page size. Each page can hold (4096 / 8) - 1 entries since the last entry must point to the next page in the pool. Signed-off-by: Aaron Williams <awilliams@marvell.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-26dm: scsi: Scan the actual number of portsPark, Aiden
The scsi_scan_dev() is looping over the number of uc_plat->max_id. The number of actual ports a AHCI controller has can be greater than max_id. Update uc_plat->max_id to make SCSI scan all detected ports. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-25mtd: nand: raw: Move CONFIG_SYS_NAND_USE_FLASH_BBT to KconfigStefan Roese
Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs, headers and whitelist. Please note that this symbol already was used in Kconfig (imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was not available in Kconfig. This changes now with this patch and all boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what I also need on my GARDENA AT91SAM based board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> [trini: Rework such that the configs are unchanged to start with] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-24Merge tag 'u-boot-rockchip-20190823' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
2019-08-24Merge branch '2019-08-23-master-imports'Tom Rini
- Migrate CONFIG_MX_CYCLIC, CONFIG_FSL_USDHC and CONFIG_MXS_GPIO to Kconfig - Fix some SPL/TPL and ARM64 dependencies
2019-08-23Convert CONFIG_FSL_USDHC to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_FSL_USDHC Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-23kconfig: Convert CONFIG_MXS_GPIO to KconfigLukasz Majewski
This converts the following to Kconfig: CONFIG_MXS_GPIO Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/571260789 Signed-off-by: Lukasz Majewski <lukma@denx.de> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-08-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clkTom Rini
2019-08-23rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang
Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23ram: rk3399: update cap and ddrconfig for each channel after initKever Yang
We need to store all the ram related cap/map info back to register for each channel after all the init has been done in case some of register was reset during the process. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-22rtc: ds3232/ds3231: Add support to generate 32KHz output for driver moduleChuanhua Han
Add an implementation of the rtc_enable_32khz_output() that uses the driver model i2c APIs. Also put code related to rtc_enable_32khz_output under CONFIG_RTC_ENABLE_32KHZ_OUTPUT. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22drivers: i2c: mxc: Fix compiler error when using i2c dm modeChuanhua Han
I2C dm mode enablemenet causes below compilation errors: In file included from include/config.h:8:0, from include/common.h:20: include/config_fallbacks.h:51:4: error: #error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" # error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" ^~~~~ In file included from include/config.h:8:0, from include/common.h:20: include/config_fallbacks.h:51:4: error: #error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" # error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used" ^~~~~ board/freescale/lx2160a/lx2160a.c: In function 'board_early_init_f': board/freescale/lx2160a/lx2160a.c:108:2: warning: implicit declaration of function 'i2c_early_init_f'; did you mean 'arch_early_init_r'? [-Wimplicit-function-declaration] i2c_early_init_f(); ^~~~~~~~~~~~~~~~ arch_early_init_r drivers/i2c/mxc_i2c.c: In function 'mxc_i2c_probe': drivers/i2c/mxc_i2c.c:824:8: warning: implicit declaration of function 'enable_i2c_clk'; did you mean 'enable_irq_wake'? [-Wimplicit-function-declaration] ret = enable_i2c_clk(1, bus->seq); ^~~~~~~~~~~~~~ enable_irq_wake So fix these compilation errors. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22boards: lx2160a: Add support of I2C driver modelChuanhua Han
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22drivers: net: mc: Report extra memory to LinuxMeenakshi Aggarwal
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved. But MC support to work with 128MB or 256MB DDR memory also, in this case, rest of the memory is not usable. So reporting this extra memory to Linux through dtb memory fixup. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22clk: imx: add i.MX8MM clk driverPeng Fan
Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: add i.MX8M composite clk supportPeng Fan
Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: add pll14xx driverPeng Fan
Add pll14xx driver for i.MX8MM usage, modifed from Linux Kernel 5.3.0-rc1 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: imx: expose CCF entry for allPeng Fan
Expose CCF entry, then we could avoid expand the SoC support list Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22sandbox: clk: add clk enable/disable test codePeng Fan
Since we added clk enable_count and prograte clk child enabling operation to clk parent, so add a new function sandbox_clk_enable_count to get enable_count for test usage. And add test code to get the enable_count after we enable/disable the device clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: prograte clk enable/disable to parentPeng Fan
On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22clk: introduce enable_countPeng Fan
As what Linux Kernel 5.3.0 provides when enable/disable clk, there is an enable_count in clk_core_disable/enable. Introduce enable_count to track the clk enable/disable count when clk_enable/disable for CCF. And Initialize enable_count to 0 when register the clk. And clk tree dump with enable_count will be supported, it will be easy for us to check the clk status with enable_count Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-22mmc: mtk-sd: Add MT8183 SoC supportFabien Parent
Add support for the MT8183 in the MediaTek MMC driver. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-08-20mmc: mtk-sd: Add MT8183 SoC supportFabien Parent
Add support for the MT8183 in the MediaTek MMC driver. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-08-19sysreset: move stm32mp sysreset poweroff implementation to sysreset uclassUrja Rannikko
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF to signal when we need it. Enable it from the STPMIC1 config and in sandbox. The config flag is transitionary, that is it can be removed after all poweroff implementations use sysreset, and just have CMD_POWEROFF depend on sysreset. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-19sysreset: switch to using SYSRESET_POWER_OFF for poweroffUrja Rannikko
It seems that SYSRESET_POWER_OFF was added recently, and all previous code used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a PMIC-level power cycle, not a poweroff. (Comment by Simon Glass) SYSRESET_POWER means to do a power reset (removing and reinstating all power) SYSRESET_POWER_OFF means to turn the device off and leave it off Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> (Update comment to help understand the patch) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19core: ofnode: do not assert if node not valid in ofnode_get_name()Kever Yang
In some case with LIVE DT, some node always not valid, or not have a valid name, eg. blk driver add by mmc. Return fail instead of Assert for this kind of ofnode, and this help with assert happen from time to time when of_live is enabled and DEBUG is enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-08-15riscv : serial: use rx watermark to indicate rx data is presentSagar Shrikant Kadam
In y-modem transfer mode, tstc/getc fail to check if there is any data available / received in RX FIFO, and so y-modem transfer never succeeds. Using receive watermark bit within ip register fixes the issue. This patch is based on commit c7392b7bc4e1 ("Use the RX watermark interrupt pending bit for TSTC") available at[1] [1] https://github.com/sifive/HiFive_U-Boot/tree/regression Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2019-08-12Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Various improvements to Keymile boards - mostly DT conversation (Pascal & Holger) - Removal of now unsupported Keymile boards (Pascal & Holger) - Small MVEBU PCI fix (Marek) - Turris Omnia defconfig update (Marek) - Misc Allied Telesis defconfig updates (Chris)
2019-08-12Merge branch '2019-08-11-ti-imports'Tom Rini
- More DaVinci updates and fixes - PCIe support on am65x - Watchdog converted to DM - Assorted other bugfixes
2019-08-12firmware: ti_sci: Parse all resource ranges even if some is not availableVignesh Raghavendra
Do not fail if any of the requested subtypes are not available, but set the number of resources to 0 and continue parsing the resource ranges. Based on Linux kernel patch by Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-08-12phy: add support for AM654x SERDESSekhar Nori
Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 can be added later. SERDES in am654x has three input clocks (left input, external reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12pcie: ti: add driver for AM65x PCIe RCSekhar Nori
Add driver supporting PCIe root-complex available on TI's AM65x SoC. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12dm: core: add support for getting register address and sizeSekhar Nori
Current dev_read_*() API lacks support to get address and size of a "reg" property by name or index. Add support for the same. Livetree support has been added but not tested on real hardware. The existing unit tests testing reading address from device-tree have been updated to test address as well as size. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12clk: add support for clk_is_match()Sekhar Nori
Add support for clk_is_match() which is required to know if two clock pointers point to the same exact physical clock. Also add a unit test for the new API. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12power: domain: ti-sci-power-domain: Add device ID info to get/set_device failureNishanth Menon
Failure log for ti_sci_power_domain_on/off is as below: "ti_sci_power_domain_on: get/set_device failed (-19)" The above information is useless for debug without information on what specific device access failed. So add that information as well. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-08-12watchdog: omap_wdt: Disable DM watchdog support in SPLSuniel Mahesh
This patch disables DM watchdog support for SPL builds and uses the legacy omap watchdog driver on TI AM335x chipsets. The following build error is reported if DM watchdog support was enabled in SPL: CC spl/drivers/usb/gadget/rndis.o LD spl/drivers/usb/gadget/built-in.o LD spl/drivers/usb/musb-new/built-in.o LD spl/drivers/built-in.o LD spl/u-boot-spl arm-linux-ld.bfd: u-boot-spl section .u_boot_list will not fit in region .sram arm-linux-ld.bfd: region .sram overflowed by 440 bytes make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 Adjusted WATCHDOG_RESET macro accordingly. Earlier it was pointing to hw_watchdog_reset. Since CONFIG_WATCHDOG replaces CONFIG_HW_WATCHDOG, now WATCHDOG_RESET macro points to watchdog_reset. This watchdog_reset is not defined anywhere for am33xx/omap2 and needs to be defined. Fixed this by simply calling hw_watchdog_reset in watchdog_reset. Built and tested on AM335x device (BeagleboneBlack), compile tested for all other AM33xx/omap2 based boards. Signed-off-by: Suniel Mahesh <sunil.m@techveda.org> [trini: Fix watchdog.h logic] Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2025-01-16 10:06:46 +0000