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2016-02-05dm: pch: Add get_io_base opBin Meng
On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: pch: Implement get_gpio_base opBin Meng
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Add get_gpio_base opBin Meng
x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Rename get_sbase op to get_spi_baseBin Meng
Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Remove pch_get_version opBin Meng
pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05spi: ich: Change PCHV_ to ICHV_Bin Meng
The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match its original name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05spi: ich: Use compatible strings to distinguish controller versionBin Meng
At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05spi: ich: Some clean upBin Meng
This cleans up the ich spi driver a little bit: - Remove struct ich_spi_slave that is not referenced anywhere - Remove ending period in some comments - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h - Add #ifndef _ICH_H_ .. in ich.h Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-02-04Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2016-02-04Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2016-02-04Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"Dinh Nguyen
Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-02-04usb: gadget: dwc2_udc_otg: modified the check condition for max packet size ↵Frank Wang
of ep_in in high speed In current high speed fastboot, fs_ep_in.wMaxPacketSize is configured 64 bytes as default, as a result, it failed to match the size at initialization stage in usb controller. Actually, hardware can support less than or equal to 512 bytes in high speed mode, so I changed the condition from '!=' to '>' to fix this issue. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Tested-by: Steve Rae <srae@broadcom.com>
2016-02-02dm: vybrid_gpio: Drop legacy codeBhuvanchandra DV
All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02dm: lpuart: Drop the legacy codeBhuvanchandra DV
All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-02Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini
2016-02-02Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
2016-02-02atmel_nand: Add 32 bit ecc support for sama5d2 chipJosh Wu
Also if minimum ecc requirment is bigger then what we support, then just use our maxium pmecc support. But it is not safe, so we'll output a warning about this. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-02atmel_nand_ecc: update pmecc registers according to sama5d2 chipJosh Wu
1. add the pmecc register mapping for sama5d2. 2. add the pmecc error location register mapping for sama5d2. 3. add some new field that is different from old ip. 4. add sama5d2 pmecc ip version number. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-01drivers: net: Add ethernet driver for Microchip PIC32.Purna Chandra Mandal
This driver implements MAC and MII layer of the ethernet controller. Network data transfer is handled by controller internal DMA engine. Ethernet controller is configurable through device-tree file. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01drivers: net: phy: add SMSC LAN8740 Phy support.Purna Chandra Mandal
Add SMSC LAN8740 Phy support required for PIC32MZDA devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-01drivers: mmc: add driver for Microchip PIC32 SDHCI controller.Andrei Pistirica
This driver implements platform specific glue and fixups for PIC32 internal SDHCI controller. Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01drivers: serial: add driver for Microchip PIC32 UART controller.Paul Thacker
This adds PIC32 UART controller support based on driver model. Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01drivers: gpio: add driver for Microchip PIC32 GPIO controller.Purna Chandra Mandal
In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01drivers: pinctrl: Add pinctrl driver for Microchip PIC32.Purna Chandra Mandal
In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.Purna Chandra Mandal
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01driver: net: fsl-mc: Update print to reflect correct stringPrabhakar Kushwaha
Update printf with dpbp_exit to match with previous function call. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-01driver: net: fsl-mc: Memset dprc_cfg before configuringPrabhakar Kushwaha
All fields of struct dprc_cfg are not being configured while creating child container. "Not" configured fields are assumed to be 0. So memset dprc_cfg before configuring the fields. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-30video: sandbox: Allow selection of font size and console nameSimon Glass
For testing it is useful to be able to select the font size and the console driver for sandbox. Add this information to platform data and copy it to the video device when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Allow selection of the driver and font sizeSimon Glass
Provide a way for the video console driver to be selected. This is controlled by the video driver's private data. This can be set up when the driver is probed so that it is ready for the video_post_probe() method. The font size is provided as well. The console driver may or may not support this depending on its capability. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2016-01-30video: Add the Cantoraone decorative fontSimon Glass
This font is a little more ornate than normal. Example uses are on security screens where a feeling of formality is required. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Add the Rufscript handwriting fontSimon Glass
This can be used when a a friendly 'hand-writing' font is needed. It helps to make the device feel familiar. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Add the AnkaCoder mono-spaced fontSimon Glass
This can be used when a mono-space font is needed, but the console font is too small (such as with high-DPI displays). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Add the Nimbus sans fontSimon Glass
This provides a good-looking font for user prompts. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Add a console driver that uses TrueType fontsSimon Glass
The existing 8x16 font is adequate for most purposes. It is small and fast. However for boot screens where information must be presented to the user, the console font is not ideal. Common requirements are larger and better-looking fonts. This console driver can use TrueType fonts built into U-Boot, and render them at any size. This can be used in scripts to place text as needed on the display. This driver is not really designed to operate with the command line. Much of U-Boot expects a fixed-width font. But to keep things working correctly, rudimentary support for the console is provided. The main missing feature is support for command-line editing. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2016-01-30video: Provide a backspace methodSimon Glass
With proportional fonts the vidconsole uclass cannot itself erase the previous character. Provide an optional method so that the driver can handle this operation. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Provide a signal when a new console line is startedSimon Glass
When we start a new line (due to the user pressing return), signal this to the driver so that it can flush its buffer of character positions. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Provide a left margin for the text consoleSimon Glass
Allow the left margin to be set so that text does not have to be right up against the left side. On some panels this makes it hard to read. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Handle the 'bell' characterSimon Glass
This can be sent when to many characters are entered. Make sure it is ignored and does not cause a character to be displayed. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-30video: Use fractional units for X coordinatesSimon Glass
With anti-aliased fonts we need a more fine-grained horizontal position than a single pixel. Characters can be positioned to start part-way through a pixel, with anti-aliasing (greyscale edges) taking care of the visual effect. To cope with this, use fractional units (1/256 pixel) for horizontal positions in the text console. Signed-off-by: Simon Glass <sjg@chromium.org> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
2016-01-30video kconfig console_normalSimon Glass
Signed-off-by: Simon Glass <sjg@chromium.org> [agust: rebased on current master] Signed-off-by: Anatolij Gustschin <agust@denx.de>
2016-01-30video: Add stb TrueType font rendererSimon Glass
This is a header file which provides a fairly light-weight TrueType rendering implementation. It is pulled from http://nothings.org/. The code style does not comply with U-Boot but I think it is best to leave alone to permit the source to be synced later if needed. The only change is to fix a reference to fabs() which should route through a macro to allow U-Boot to provide its own version. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-29Merge git://git.denx.de/u-boot-dmTom Rini
2016-01-28Implement "pci enum" command for CONFIG_DM_PCIStephen Warren
With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they are without that config option enabled. No command exists to enumerate the PCI buses. Hence, unless some board-specific code causes PCI enumeration, PCI-based Ethernet devices are not detected, and network access is not available. This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a mechanism whereby PCI can be enumerated. do_pci()'s handling of case 'e' is moved into a single location before the dev variable is assigned, in order to skip calculation of dev. The enum sub-command doesn't need the dev value, and skipping its calculation avoids an irrelevant error being printed. Using a command to initialize PCI like this has a disadvantage relative to enumerating PCI at boot. In particular, Ethernet devices are not probed during PCI enumeration, but only when used. This defers setting variables such as ethact, ethaddr, etc. until the first network-related command is executed. Hopefully this will not cause further issues. Perhaps in the long term, we need a "net start/enum" command too? Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28dm: Remove device_probe_child()Simon Glass
This function is not used as the use case for it did not eventuate. Remove it to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28tpm: st33zp24: Add tpm st33zp24 spi supportChristophe Ricard
Add support for TPM ST33ZP24 spi. The ST33ZP24 does have a spi interface. The transport protocol is proprietary. For spi we are relying only on DM_SPI. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
2016-01-28tpm: st33zp24: Add tpm st33zp24 support with i2cChristophe Ricard
Add support for TPM ST33ZP24 family with i2c. For i2c we are relying only on DM_I2C. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
2016-01-28tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific stuff ↵Christophe Ricard
in tpm_infineon.c I2C protocol is not standardize for TPM 1.2. TIS prococol is define by the Trusted Computing Group and potentially available on several TPMs. tpm_tis_infineon.h header is not generic enough. Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific defines/variables to tpm_tis_infineon.c Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
2016-01-28tpm: tpm_tis_lpc: fix typoChristophe Ricard
TPM_TIS_LPC is connected to the LPC bus, not I2C. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
2016-01-28Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
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