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On modern NAND it's more than recommended to have a backup copy of the
u-boot binary to recover from corruption: bitflips are quite common on
MLC NANDs, and the read-disturbance will corrupt your u-boot partitition
more quickly than what you would see on an SLC NAND.
Add an extra Kconfig option to specify the offset of the redundant u-boot
image.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
[scottwood: added ifdef to fix build break]
Signed-off-by: Scott Wood <oss@buserror.net>
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The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced
to explicitly depend on platforms that are not already defining it in their
include/configs/<board>.h header.
Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS
depends on it, remove the dependency on NAND_SUNXI and make it dependent
on SPL selection.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
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The sunxi SPL NAND controller driver supports use 'BootROM'-like configs,
that is, configs where the ECC bytes and real data are interleaved in the
page instead of putting ECC bytes in the OOB area.
Doing that has several drawbacks:
- since you're interleaving data and ECC bytes you can't use the whole page
otherwise you might override the bad block marker with non-FF bytes.
- to solve the bad block marker problem, the ROM code supports partially
using the page, but this introduces a huge penalty both in term of read
speed and NAND memory usage. While this is fine for rather small
binaries(like the SPL one which is at maximum 24KB large), it becomes
non-negligible for the bootloader image (several hundred of KB).
- auto-detection of the page size is not reliable (this is in my opinion
the biggest problem). If you get the page size wrong, you'll end up
reading data at a different offset than what was specified by the caller
and the reading may succeed (if valid data were written at this address).
For all those reasons I think it's wiser to completely remove support for
'syndrome' configs. If we ever need to support it again, then I'd recommend
specifying all the config parameters through Kconfig options.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
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The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
provider now implements a single set of clocks. This provides a simpler
conceptual interface to clients, and better aligns with device tree
clock bindings.
* Clocks are now identified with a single "struct clk", rather than
requiring clients to store the clock provider device and clock identity
values separately. For simple clock consumers, this isolates clients
from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
clk-uclass.h contains the provider API. This aligns with the recently
added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
can customize these operations if needed. This also aligns with the
recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.
Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.
test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This adds a sandbox reset implementation (provider), a test client
device, instantiates them both from Sandbox's DT, and adds a DM test
that excercises everything.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.
This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.
The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Tegra186's HSP module implements doorbells, mailboxes, semaphores, and
shared interrupts. This patch provides a driver for HSP, and hooks it
into the mailbox API. Currently, only doorbells are supported.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
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Rename mailbox*.h to match the naming convention requested during review
of the new reset subsystem.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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A bug in the pca953x driver prevents correct reading of GPIO input
values beyond the 8th GPIO; all values are reported as zero. Setting of
GPIO output values is not affected.
This patch fixes the reading behavior.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Some architectures as m68k still need to use CONFIG_NEEDS_MANUAL_RELOC,
and are not still using the device tree.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Acked-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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If the usb controller is not running, no need to shutdown it,
otherwise `usb stop` complains about:
"EHCI failed to shut down host controller".
To i.MX7D SDB, there are two usb ports, one Host, one OTG.
If we only plug one udisk to the Host port and then `usb start`,
the OTG controller for OTG port does not run actually. Then,
if `usb stop`, the OTG controller for OTG port will also be
shutdown, but it is not running.
This patch adds a check to only shutdown the running controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: "Stefan Brüns" <stefan.bruens@rwth-aachen.de>
Cc: Stephen Warren <swarren@nvidia.com>
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This patch is doing the following:
1. Implementing the errata for LS2080.
2. Adding fixup for fdt for LS2080.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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This patch does the following things:
1. Makes the errata checking code common for PPC and ARM
2. Moves all these static inline functions into a dedicated C file
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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Performs code cleanup for device tree fixup for fsl usb controllers by
making functions to handle these similar errata checking code.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
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Define CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 to allow the
physical interface to be 8-bit (rather than 16-bit).
Signed-off-by: Steve Rae <srae@broadcom.com>
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Add initial support for NXP's S32V234 SoC and S32V234EVB board.
The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.
Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
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The Linflex module is integrated on some NXP automotive SoCs part of the former
Freescale portfolio, like S32V234, an SoC for Advanced Driver Assistance
Systems.
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Chircu Bogdan <Bogdan.Chircu@freescale.com>
Original-signed-off-by: Depons Eric <eric.depons@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>
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Add device tree support.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add driver-model support to this driver. Most features can be controlled
from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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Adjust the driver to use struct display_timing for its display timing.
This is what is used by driver-model and allows the LCD init code to be
common.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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This needs to be set to avoid a fatal error when ECC is used.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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This uses the wrote base register value. Fix it.
Signed-off-by: Andre Renaud <andre@designa-electronics.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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Add driver-model support to this driver. The old code remains for now so
that we can convert boards one at a time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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Adjust this driver to avoid using struct netdev in functions that driver
model will call. Also refactor the receive function to be compatible with
driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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On systems with PIO3 (SAMA5D3/D4/..), the pullup and pulldown configuration
is mutualy exclusive. This patch assures that the opposite pull resistor gets
disabled before the requested pull resistor is enabled. This changes behavior
of at91_set_pio_pulldown() such that the pullup is only disabled if pulldown
is to be enabled. This changes behavior of at91_set_pio_pullup() such that
the pulldown is only disabled if pullup is to be enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.
The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256
In this example, SHA256 is the only selected hashing algorithm.
And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y
Signed-off-by: Teddy Reed <teddy.reed@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
Acked-by: Sumit Garg <sumit.garg@nxp.com>
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Now that we have set up pin control in cpu_init_r(), remove the
duplicated codes in the broadwell gpio driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:
- Pin's PADs only gets configured when GPIO driver is probed, which
is not done by default. This leaves the board in a partially
functional state as we must initialize PADs correctly to get
perepherals fully working.
- The probe routine of pinctrl driver is called multiple times, as
normally there are multiple GPIO controllers. It should really
be called just once.
Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
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The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controlling respective pin as gpio ('cs-gpios' property in dt node)
and uses PIO mode for SPI transaction. It is configurable based
on driver-model only.
Cc: Jagan Teki <jteki@openedev.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Turn of the clock and assert the reset when musb_stop gets called, so that
the os gets the musb controller in a pristine state. This fixes a spurious
VBus error interrupt triggering as soon as the Linux musb driver loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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writting to ubi nand partitions need after write ends an erase
of the remaining sectors. This fail, if dfu write size was not
a multiple of erasesize, example log:
Failure erase: -1
Fix this error.
Signed-off-by: Heiko Schocher <hs@denx.de>
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support in omap_nand_switch_ecc() also an eccstrength
from 16.
Signed-off-by: Heiko Schocher <hs@denx.de>
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add for nand devices mtd concat support. Generic MTD concat
support is already ported to mainline, and used in the cfi_mtd
driver. This patch adds it similiar for nand devices.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
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revert patch:
commit: 6b2221b008e0: mmc: Handle switch error status bit in MMC card status
to get eMMC working on shc board
Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
configs/peach-pi_defconfig
configs/peach-pit_defconfig
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Modified:
configs/ls1012afrdm_qspi_defconfig
configs/ls1012aqds_qspi_defconfig
configs/ls1012ardb_qspi_defconfig
include/configs/ls1012afrdm.h
include/configs/ls1012aqds.h
include/configs/ls1012ardb.h
Signed-off-by: Tom Rini <trini@konsulko.com>
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Add some tests for the new open drain setting feature of the GPIO
uclass, and extend the capabilities of the sandbox GPIO driver
accordingly.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
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