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2019-03-04pinctrl: renesas: r8a77990: Fix rename RTSx_N_TANS_x to RTSx_N_xHiroyuki Yokoyama
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR / MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndfHiroyuki Yokoyama
This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22] of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Remove r8a779{5,6,65} CC5_OSCOUT of IP17Hiroyuki Yokoyama
This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795 / r8a7796 / r8a77965. This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Fix r8a779{5,6,65} rename sel_adg_ to sel_adgHiroyuki Yokoyama
This patch fixes to the correct names, and "_" is not include after "adg" for r8a7795/r8a7796/r8a77965. This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Fix r8a779{5,6,65} assign to GP7_03/02 of GPSR7Hiroyuki Yokoyama
This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03", and "HDMI0_CEC" to "GP7_02". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- SoCFPGA cache/gpio fixes
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28spi: omap3: fix set_wordlen() reading from incorrect address for CHCONFDavid Rivshin
_omap3_spi_set_wordlen() indexed the regs->channel[] array with the old wordlen (instead of the chipselect number) when reading the current CHCONF register value. This meant it read from the wrong memory location, modified that value, and then wrote it back to the correct CHCONF register. The end result is that most slave configuration settings would be lost, such as clock divisor, clock/chipselect polarities, etc. Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin <drivshin@allworx.com>
2019-02-27cpu: Bind timer driver for boot hartAtish Patra
Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27drivers: serial_sifive: Skip baudrate config if no input clockAtish Patra
It is possible that input clock is not available because clk device was not available and 'clock-frequency' DT property is also not available. In this case, instead of failing we should just skip baudrate config by returning zero. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-27drivers: serial_sifive: Fix baud rate calculationAtish Patra
Compute the baud rate multipler with more precision. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27clk: Add fixed-factor clock driverAnup Patel
This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27clk: Add SiFive FU540 PRCI clock driverAnup Patel
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-27net: macb: Fix GEM hardware detectionAtish Patra
Fix MID bit field check to correctly identify all GEM hardwares. The check is updated as per macb driver in Linux location: <linux_sources>/drivers/net/ethernet/cadence/macb_main.c:259 Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27net: macb: Fix clk API usage for RISC-V systemsAnup Patel
Don't fail in macb_enable_clk() if clk_enable() returns -ENOSYS because we get -ENOSYS for fixed-rate clocks. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8Marek Vasut
According to latest specification rev.0026 and after confirmation with HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on H3 ES2.0 SoC. Make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25mmc: tmio: Clear BUSWIDTH bit when WMODE bit is setMarek Vasut
According to latest specification rev.0026, when HOST_MODE bit 0 (WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear HOST_MODE bit 8 in such case and align the code with Linux and avoid possible unforeseen issues. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25pinctrl: renesas: Drop def_bool per SoCMarek Vasut
Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25clk: rmobile: Drop def_bool per SoCMarek Vasut
Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25gpio: altera_pio: fix get_valueJulien Béraud
gpio_get_value should return 0 or 1, not the value of bit & (1 << pin) Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
2019-02-20Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2019-02-20Merge git://git.denx.de/u-boot-x86Tom Rini
- Add support for sound. Albeit the big changeset, changes are pretty limited to x86 only and a few new sound drivers used by x86 so I think it would be good to have this in the next release.
2019-02-20Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
- Support of NXP's LX2160RDB and LX2160QDS platform - Enable SATA DM model for NXP's ARM SoCs
2019-02-20Kconfig: tegra: Migrate TEGRA_KEYBOARDPeter Robinson
Migrate TEGRA_KEYBOARD from headers to Kconfig, only the seaboard uses it but we drop CONFIG_KEYBOARD as the driver doesn't use the legacy drv_keyboard_init. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20Kconfig: tegra: Migrate USB_EHCI_TEGRAPeter Robinson
Migrate USB_EHCI_TEGRA from headers to Kconfig Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peter.Chubb@data61.csiro.au Cc: Lucas Stach <dev@lynxeye.de> Cc: Stefan Agner <stefan.agner@toradex.com> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20Kconfig: tegra: Migrate SYS_I2C_TEGRAPeter Robinson
Migrate SYS_I2C_TEGRA from headers to Kconfig Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Heiko Schocher <hs@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peter.Chubb@data61.csiro.au Cc: Lucas Stach <dev@lynxeye.de> Cc: Stefan Agner <stefan.agner@toradex.com> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20x86: Add sound support for samusSimon Glass
Enable sound on samus using the broadwell I2S and an RT5677 audio codec. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-20x86: sound: Add sound support for samus (broadwell)Simon Glass
Add a sound driver for samus which ties together the audio codec and I2S controller. For now broadwell_sound is commented out in the makefile since we cannot compile it without sound support enabled. The next commit fixes this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: Add a driver for RealTek RT5677Simon Glass
This audio codec is used on samus. Add a driver for it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: sound: Add support for broadwell I2SSimon Glass
I2S is used to send digital audio data to an audio codec. Add support for this on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: Add a driver for the i8254 beepSimon Glass
Add a sound driver which can output simple beeps using this legacy timer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: link: Add sound supportSimon Glass
Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sandbox: sound: Silence sound for testingSimon Glass
When testing the sound system we don't need the hear the beeps. The testing works by checking the data that would be emitted. Add a device-tree property to silence the sound, and enable it for testing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: Add support for Intel HDASimon Glass
The Intel High-definition Audio is a newer-generation audio system which provides for transfer of a large number of audio stream, each containing up to 16 channels. Add support for HDA as a library which can be used by other drivers. U-Boot currently uses only two channels (stereo). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: Add uclass operations for beepingSimon Glass
Some audio codecs such as Intel HDA do not need to use digital data to play sounds, but instead have a way to emit beeps. Add this interface as an option. If the beep interface is not supported, then the sound uclass falls back to the I2S interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: Mark sound_setup() as optionalSimon Glass
This method in the sound API is optional since some drivers can do this when probing or as part of SoC init. Mark it as such. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20pch: Add ioctl supportSimon Glass
At present the PCH has 4 operations and these are reasonably widely used in the drivers. But sometimes we want to add rarely used operations, and each of these currently adds to the size of the PCH operations table. Add an ioctl() method which can be easily expanded without any more impact on the operations table. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sandbox: pch: Add a test for the PCH uclassSimon Glass
This uclass currently has no tests. Add a sandbox driver and some simple tests to provide basic coverage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: Use "sandbox,pch" for the compatible string, for consistency] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: sandbox: pch: Add a CONFIG option for PCHSimon Glass
At present this uclass is selected only on x86. In order to add a test for it, it must also support sandbox. Create a new CONFIG_PCH option and enable it on x86 and sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20pci: Don't export pci_hose_config_device()Simon Glass
This function is not used outside this file so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20i2c: designware: Add error checking on initSimon Glass
At present this driver does not check whether it is able to actually communicate with the I2C controller. It prints a timeout message but still considers the probe to be successful. To fix this, add some checking that the init succeeds. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-20dm: syscon: Don't require a regmap for PCI devicesSimon Glass
At present it is not possible to use the syscon devices for PCI devices since a regmap is required. Since PCI uses a 3-cell address the conversion of the 'reg' property to an address always fails. In any case, the regmap is not useful with PCI since devices are accessed through the PCI bus which regmap does not support. Add a special case for PCI syscon devices, so that they don't set up a regmap. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-19dm: scsi: report correct device numberHeinrich Schuchardt
Before the patch scsi would report the same device number for all SCSI devices, e.g. Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) Device 0: (1:0) Vendor: ATA Prod.: Rev: Type: Hard Disk Capacity: not available With the patch the same device number is reported as is used in scsi_read(): Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) Device 1: (1:0) Vendor: ATA Prod.: Rev: Type: Hard Disk Capacity: not available Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-19drivers/ddr/fsl: Update fsl_ddr_board_options as weak functionPriyanka Jain
fsl_ddr_board_options is generally defined in board board's ddr.c, but some boards like lx2160ardb board does not need this function. Defining fsl_ddr_board_options as weak function to resolve compilation errors for such boards. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Fix checkpatch warnings] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-18Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Misc Gen5 fixes - stratix10 bugfix - dwmmc bugfix
2019-02-18ARM: socfpga: stratix10: Return valid error code from FPGA driverAng, Chee Hong
This patch prevent the Stratix 10 FPGA driver incorrectly return the transaction ID as the mailbox error code. It should always return the actual mailbox error code from SDM firmware. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-02-18mmc: dwmmc: Poll for iDMAC TX/RX interruptLey Foon Tan
Poll for iDMAC TX/RX interrupt before disable DMA. This to prevent disable DMA before data is transfer completed. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-02-18arm: socfpga: gen5 enable designware_socfpgaSimon Goldschmidt
Enable the socfpga specific designware ethernet driver by default for socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a MACH_SOCFPGA config. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18net: designware: socfpga: adapt to Gen5Simon Goldschmidt
This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-16Merge tag 'video-for-2019.04-rc2' of git://git.denx.de/u-boot-videoTom Rini
- sunxi display DDC probe fallback - support 24bpp BMP files on 16bpp displays
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