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2016-01-20serial: lpuart: Add driver model serial supportBin Meng
This adds driver model support to lpuart serial driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Tested-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2016-01-20serial: lpuart: Prepare the driver for DM conversionBin Meng
Create internal routines which take lpuart's register base as a parameter, in preparation for driver model conversion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20serial: lpuart: Call local version of setbrg and putc directlyBin Meng
There is no need to go through serial driver subsystem, instead call the driver's setbrg and putc routines directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20serial: lpuart: Fix several cosmetic issuesBin Meng
Clean up the driver codes a little bit, by: - Use tab instead of space in the macro defines - Use single line comment whenever possible - Fix insertion of blank lines Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20serial: lpuart: Move CONFIG_FSL_LPUART to KconfigBin Meng
LPUART is seen on Freescale VF610 and QorIQ Layerscape devices. Create a Kconfig option and move it to defconfig for all boards that have this serial driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20clk: add API to enable clockMasahiro Yamada
The most basic thing for clock is to enable it, but it is missing in this uclass. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20clk: add static qualifier to local functionsMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20clk: move Kconfig options into sub-menuMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20timer: sandbox: work without device treeStephen Warren
A default invocation of sandbox U-Boot apparently uses no device tree, which means that no timer is registers, which in turn means that the sleep shell command hangs. Fix the sandbox timer code to register a device when there's no DT, just like e.g. the sandbox reset driver does. When there's no DT, the DM uclass can't initialize clock_rate from DT, so set a default value in the timer code instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: timer: refuse timers with zero clock_rateStephen Warren
If a timer has a zero clock_rate, get_tbclk() will return zero for it, which will cause tick_to_time() to perform a division-by-zero, which will crash U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: core: Call uclass post_bind() after the driver's bind() methodSimon Glass
At present the uclass's post_bind() method is called before the driver's bind() method. This means that the uclass cannot use any of the information set up by the driver. Move it later in the sequence to permit this. This is an ordering change which is always fairly major in nature. The main impact is that devices which have children will not see them appear in their bind() method. From what I can see, existing drivers do not look at their children in the bind() method, so this should be safe. Conceptually this change seems to result in a 'more correct' ordering, since the uclass (which is broader than the device) gets the last word. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-20pinctrl: Avoid binding all pinconfig nodes before relocationSimon Glass
This can create a large number of pinctrl devices. It chews up early malloc() memory and takes time. Only bind those which are marked as needed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: mmc: Try to honour the sequence orderSimon Glass
At present we add driver-model MMC devices in the order we find them. The 'alias' order is not honoured. It is difficult to fix this for the case where we have holes in the sequence. But for the common case where the devices are numbered from 0 without any gaps, we can add the devices to the internal data structures in this order. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: gpio: Allow the uclass to work without printf()Simon Glass
For SPL we don't really need sprintf() and with tiny-printf this is not available. Allow this to be dropped in SPL when using tiny-printf. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20drivers: timer: omap_timer: add timer driver for omap devices based on dmMugunthan V N
Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-01-20dm: timer: uclass: Add flag to control sequence numberingMugunthan V N
Like SPI and I2C, timer devices also have multiple chip instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in timer_uclass driver to control device sequence numbering. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-20dm: timer: uclass: add timer init in uclass driver to add timer deviceMugunthan V N
Adding timer init function in timer-uclass driver to create and initialize the timer device on platforms where u-boot,dm-pre-reloc is not used. Since there will be multiple timer devices in the system, adding a tick-timer node in chosen node to know which timer device to be used as tick timer in u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-01-20dm: core: Provide uclass_find_device_by_phandle() only when neededSimon Glass
This function cannot be used unless support is enabled for device tree control. Adjust the code to reflect that. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-20spi: ti_qspi: Use 4-byte opcode for mmap readVignesh R
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB. Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB. Signed-off-by: Ravi Babu <ravibabu@ti.com> [vigneshr@ti.com: Re-word commit description] Signed-off-by: Vignesh R <vigneshr@ti.com>
2016-01-19arm: serial: Add Kconfig entries to facilitate usage of the pl01x driver for ↵Sergey Temerkhanov
early debug output This patch adds Kconfig entries to facilitate usage of pl01x as a debug UART. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-19arm: serial: Add debug UART capability to the pl01x driverSergey Temerkhanov
This patch adds an ability to use pl01x as a debug UART. It must be configured like other types of debug UARTs Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> [trini: Update for _debug_uart_init change] Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini
2016-01-19power: regulator: max77686: Don't use switch() on boolsTom Rini
With gcc-5.3 we get a warning for using switch() on a bool type. Rewrite these sections as if/else and update the one section that was using 1/0 instead of true/false. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
2016-01-19spi: rk_spi: Fix debug format warningTom Rini
We need to use %lx not %x to describe a fdt_addr_t Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19pci_rom.c: Fix may be used uninitialized warningTom Rini
With gcc-5.x we get: drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios': drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in this function [-Wmaybe-uninitialized] While unconvinced that this can happen in practice (if we malloc we set alloced to true, it will be false otherwise), silence the compiler. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-19Add more SPDX-License-Identifier tagsTom Rini
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-16Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2016-01-16net: pcnet: refactor mapping of virtual addresses to physical onesDaniel Schwierzeck
pci_virt_to_mem() uses virt_to_phys() to get the physical address. But pci_virt_to_mem() is also called with uncached addresses which is wrong according to the documentation of virt_to_phys(). Refactor the PCI_TO_MEM() macro to optionally map an uncached address back to a cached one before calling pci_virt_to_mem(). Currently pcnet works because virt_to_phys() is incorrectly implemented on MIPS. With the upcoming asm header file update for MIPS, the virt_to_phys() implementation will be fixed. Thus this patch is needed to keep pcnet working on MIPS Malta board. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2016-01-16arm: socfpga: set the fpga global bit to disable HPS to FPGA signalsDinh Nguyen
We should be setting the FPGA Interface Group global bit that will correctly disable all interfaces between the FPGA and HPS. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-01-16ddr: altera: Init the rule ID in debug codeMarek Vasut
Init the rule ID, otherwise the debug code will always dump the protection settings entry 0. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com>
2016-01-16usb: host: ehci-vf: Implement board_usb_phy_mode weak functionSanchayan Maity
Add board_usb_phy_mode weak function on similar lines to ehci-mx6. However since Vybrid USB does not have a true OTG, make this weak functon just return 0. The function is supposed to be implemented by the individual boards using a GPIO for providing the OTG pin functionality. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2016-01-16usb: host: ehci-vf: Remove hardcoded USB host client configurationSanchayan Maity
The current ehci-vf USB driver for Vybrid hardcodes the USB host and client functionality. Remove this. Reported-by: Santhosh Kumar Janardhanam <santhosh.kj@hcl.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2016-01-16usb:ci_udc: Remove ULPI setting for i.MX OTG controllerYe.Li
All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface. Set to ULPI is not correct, even the controller will reject this setting in PORTSC register. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2016-01-15Merge git://git.denx.de/u-boot-rockchipTom Rini
2016-01-15dm: pci: Avoid a memory leak when allocating the ROMSimon Glass
Adjust pci_rom_load() to return an indication of whether it allocated memory or not. Adjust the caller to free it. This fixes a memory leak when PCI_VGA_RAM_IMAGE_START is not used. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-15dm: pci: Add a 'fall through' commentSimon Glass
For this class it is intended to set up the PCI device, so add a comment to indicate this. This avoids a coverity warning. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-15dm: spi_flash: Allow the uclass to work without printf()Simon Glass
For SPL we don't really need sprintf() and with tiny-printf this is not available. Allow this to be dropped in SPL when using tiny-printf. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-15mmc: rockchip: the non-removable property must point to emmchuang lin
the non-removable property point to sdcard before, it is wrong, it must point to emmc, correct it. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-14Fix GCC format-security errors and convert sprintfs.Ben Whitten
With format-security errors turned on, GCC picks up the use of sprintf with a format parameter not being a string literal. Simple uses of sprintf are also converted to use strcpy. Signed-off-by: Ben Whitten <ben.whitten@gmail.com> Acked-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14Merge git://www.denx.de/git/u-boot-marvellTom Rini
Conflicts: arch/arm/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-14mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter
This should make it clear that this symbol is meant to be defined by board headers. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14drivers/pci/pci_mvebu: Fix for boards with X4 lanesPhil Sutter
Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14axp: Fix debugging support in DDR3 write levelingPhil Sutter
If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing. In addition to that, get rid of debug output printing non-existent counter variable. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14drivers/pci: Fix for debug builds without CONFIG_PCI_ENUM_ONLYPhil Sutter
The debug printing references bar_res, which exists only if CONFIG_PCI_ENUM_ONLY is not defined. Therefore move it into the ifdef'd area. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14arm: mvebu: Move SoC selection (A38X vs AXP) into KconfigStefan Roese
Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14arm: mvebu: Make ECC support configurable on Armada XPStefan Roese
Currently, ECC support is enabled for all Armada XP boards. So the DDR3 driver tries to configure the controller with ECC support, even on boards without ECC. This patch makes this ECC optional which now can be configured on a board-per-board basis. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
2016-01-14sata: Add SATA driver with DMA support for Marvell Kirkwood and Armada XPTor Krill
This patch adds a new SATA driver for the Marvell Kirkwood and Armada 370 / XP SoC's. This driver supports the SATA controller of some Mavell SoC's. Here a (most likely incomplete) list of the supported SoC's: - Kirkwood - Armada 370 - Armada XP This driver implementation is an alternative to the already available driver via the "ide" commands interface (drivers/block/mvsata_ide.c). But this driver only supports PIO mode and as this new driver also supports transfer via DMA, its much faster. Please note, that the newer SoC's (e.g. Armada 38x) are not supported by this driver. As they have an AHCI compatible SATA controller integrated. The original version of this driver was sent by Tor Krill to the U-Boot list a few years ago. Here the link: http://lists.denx.de/pipermail/u-boot/2010-June/073147.html Changes by Stefan: - Coding-style cleanup - Support for Armada XP added - MBUS window setup added - D-cache flush and invalidation added - works with dcache enabled on Armada XP - Removed mdelay() from ata_wait_register() and add timer based timeout detection to speed up the transfer Signed-off-by: Tor Krill <tor@excito.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com>
2016-01-14net: mvneta: Convert to driver modelStefan Roese
Update this driver to support driver model. As all MVEBU boards using this driver are converted with this patch, the non-driver-model code can be removed completely. This is also the reason why this patch is quite big and includes a) the driver change and b) the platform change. As its not git-bisect save otherwise. With this conversion, some parameters are now extracted from the DT instread of using the config header defines. The supported properties right now are: PHY-mode ("phy-mode") and PHY-address ("reg"). The base addresses for the ethernet controllers can be removed from the header files as well. Please note that this patch also removes the E1000 network driver from some MVEBU config headers. This is necessary, as with DM_ETH configured and the e1000 driver enabled, the PCI driver also needs to support DM. But the MVEBU PCI(e) driver still needs to get ported to DM. When this is done, the E1000 driver can be enabled again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
2016-01-14spi: kirkwood_spi.c: Add driver model supportStefan Roese
This patch adds driver model support to the kirkwood SPI driver. Which is also used on the MVEBU SoC's, now being converted to DM. Non-DM support is still available for the "older" platforms using this driver, like kirkwood. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-10 15:51:55 +0000