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2020-07-14clk: imx8m: drop clk settingsPeng Fan
We use non-dm code to configure the clk settings in order to simplify dm clk driver in future, so remove the duplicated code from clk driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14clk: imx8mp: Update imx8mp ccf clock driverYe Li
Add clocks for FEC and flexspi, and add set parent clock callback, so DTS can assign clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14clk: imx8mm/8mn: Add USB clocksYe Li
Add USB relevant clocks to support usb clock settings for both DM USB host and gadget drivers Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14clk: clk-imx8mn: Update clock tree and support set parentYe Li
Add set clock parent support. Add ENET and flexspi related clocks to support assigned clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14clk: imx8mm: Add qspi clockPeng Fan
Add qspi clock Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14clk: imx8mm: fix clk set parentPeng Fan
Fix clk set parent, so we could still have correct clocks after parent changing. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14imx: power-domain: use arm_smccc_smcPeng Fan
Use arm_smccc_smc to replace call_imx_sip Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14imx8: fuse: use arm_smccc_smcPeng Fan
Use arm_smccc_smc to replace call_imx_sip Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14pinctrl: imx5: move soc info to data sectionPeng Fan
The soc info without initialization value should be put into data section. The driver could be used before relocation, with it in BSS section could cause issue, since BSS section is not initializated and it might overwrite other areas that used by others, such as dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14pinctrl: imx8m: move soc info to data sectionPeng Fan
The soc info without initialization value should be put into data section. The driver could be used before relocation, with it in BSS section could cause issue, since BSS section is not initializated and it might overwrite other areas that used by others, such as dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14pinctrl: imx7: move soc info to data sectionPeng Fan
The soc info without initialization value should be put into data section. The driver could be used before relocation, with it in BSS section could cause issue, since BSS section is not initializated and it might overwrite other areas that used by others, such as dtb. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issueOliver Chen
Add logic to automatically update umctl2's setting based on phy training CDD value for rank to rank space issue Acked-by: Ye Li <ye.li@nxp.com> Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14drivers: ddr: imx8mp: Add inline ECC feature supportSherry Sun
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8mJacky Bai
The 'selfref_en' should be bit'0', so correct the setting to enable the auto self-refresh. Reviewed-by: Jian Li <jian.li@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14driver: ddr: imx: skip ddr_ss_gpr config on imx8mnJacky Bai
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting this register on i.MX8MN. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-13mmc: omap_hsmmc: Set 3.3V for IO voltage on all placesPali Rohár
In commit commit d2c05f50e12f ("mmc: omap_hsmmc: Set 3.3V for IO voltage") was changed 3.0V IO voltage to 3.3V but it was not done on all places in omap_hsmmc driver. That commit broke eMMC support on Nokia N900. This patch fixes that problematic commit and changes 3.0V to 3.3V on all remaining places in omap_hsmmc driver. Fixes: d2c05f50e12f ("mmc: omap_hsmmc: Set 3.3V for IO voltage") Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
2020-07-13net: ti: am65-cpsw-nuss: Update driver to use kernel DTVignesh Raghavendra
Kernel DT has CPSW ports under ethernet-ports subnode. Update the driver to look for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13net: ti: am65-cpsw-nuss: Set ALE default thread enableVignesh Raghavendra
Force default thread to be used for RX as ALE is anyways set to Bypass mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13net: ti: am65-cpsw-nuss: Remove dead codeVignesh Raghavendra
MDIO node is not referenced further, therefore drop the dead code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Switch to k3_ringacc_request_rings_pairVignesh Raghavendra
We only request ring pairs via K3 DMA driver, switch to use the new k3_ringacc_request_rings_pair() to simplify the code. As a good side effect, all boot stages now use exposed RING mode which avoid maintaining proxy mode for 32 bit R5 core. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Move RX descriptor ring entries to rflow structVignesh Raghavendra
In K3 UDMA architecture, RX rings are associated with RX flows rather than RX channels, therefore move the ring pointers to udma_rflow struct Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Introduce udma_chan_config structVignesh Raghavendra
Encapsulate channel configuration in a separate struct so as to ease resetting of these fields with memset() and also to increase readability of the code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13soc: ti: k3-ringacc: Separate soc specific initializationVignesh Raghavendra
In preparation of adding more K3 SoCs, separate soc specific initialization add a SoC specific initialization hook. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13soc: ti: k3-ringacc: Add an API to request pair of ringsVignesh Raghavendra
Add new API k3_ringacc_request_rings_pair() to request pair of rings at once, as in the most case Rings are used with DMA channels which required to request pair of rings - one to feed DMA with descriptors (TX/RX FDQ) and one to receive completions (RX/TX CQ). This will allow to simplify Ringacc API users. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13soc: ti: k3-ringacc: Move state tracking variables under a structVignesh Raghavendra
Move the free, occ, windex and rinfex under a struct. We can use memset to zero them and it will allow a cleaner way to extend the variables for duplex rings. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13dma: ti: k3-udma: Update driver to use static endpoint DataVignesh Raghavendra
Update driver to use static PSIL endpoint Data instead of DT. This will allow DT bindings to be in sync with kernel's DT. Note that this patch breaks networking and OSPI boot as driver changes are not backward compatible with existing DT. Subsequent commit will update the DT to make it compatible with updated driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-13dma: ti: Add static PSIL endpoint informationVignesh Raghavendra
Much of PSIL endpoint configuration for a given SoC can be known at compile time, therefore pass them for platform specific data instead of DT. Add per SoC's specific PSIL endpoint data. This is to bring driver in sync with upstream DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-11Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- Enable DM_SPI on siemens omap boards (Jagan) - Dropped some non-dm supported omap3 boards (Jagan) - Dropped non-dm code in omap3 spi driver (Jagan) - Dropped non-dm code in kirkwood spi driver (Bhargav)
2020-07-11Merge tag 'uniphier-v2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.10 - remove workaround for Cortex-A72 - increase U-Boot proper size to 2MB - sync DT with Linux - add system bus controller driver - improve serial driver - add reset assertion to Denali NAND driver
2020-07-11mtd: nand: raw: denali: Wait for reset completion statusLey Foon Tan
Fixed delay 200us is not working in certain platforms. Change to poll for reset completion status to have more reliable reset process. Controller will set the rst_comp bit in intr_status register after controller has completed its reset and initialization process. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11mtd: nand: raw: denali: Assert reset before deassertLey Foon Tan
Always put the controller in reset, then take it out of reset. This is to make sure controller always in reset state in both SPL and proper Uboot. This is preparation for the next patch to poll for reset completion (rst_comp) bit after reset. Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Radu Bacrau <radu.bacrau@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11serial: uniphier: enable FIFOMasahiro Yamada
This UART controller is integrated with a FIFO. Enable it. You can put the next character into the FIFO while the transmitter is sending out the current character. This works slightly faster. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11serial: uniphier: flush transmitter before changing hardware settingsMasahiro Yamada
Ensure the transmitter is empty when chaining the baudrate or any hardware settings. If a character is remaining in the transmitter, the console will be garbled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11serial: uniphier: use register macros instead of structureMasahiro Yamada
After all, I am not a big fan of using a structure to represent the hardware register map. You do not need to know the entire register map. Add only necessary register macros. Use FIELD_PREP() instead of maintaining a pair of shift and mask. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: move hardware init from board filesMasahiro Yamada
Move the bus initialization code to this driver from board files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11bus: uniphier-system-bus: add UniPhier System Bus driverMasahiro Yamada
Since commit 1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based drivers/net/smc911x.c is compiled, but it is never probed because the parent node lacks the DM-based driver. I need a skeleton driver to populate child devices (but the next commit will move more hardware settings to the this driver). I put this to drivers/bus/uniphier-system-bus.c because this is the same path as the driver in Linux kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-10Merge tag 'dm-pull-10jul20' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata: better phandle and compatible-string support patman support for Python3 on Ubuntu 14.04 new checkpatch check to avoid #ifdefs
2020-07-10Merge tag 'rpi-next-2020.10' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - add support for PCI and XHCI for RPi4 (64 bit only) - optionally reset XHCI device on registration - enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10mmc: bcm283x: fix int to pointer castSeung-Woo Kim
On build with 32 bit, there is a warning for int-to-pointer-cast. Fix the int to pointer cast by using uintptr_t. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2020-07-10usb: xhci: Add reset controller supportNicolas Saenz Julienne
Some atypical users of xhci might need to manually reset their xHCI controller before starting the HCD setup. Check if a reset controller device is available to the PCI bus and trigger a reset. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> [mb: squash fix to only build xhci_reset_hw() if CONFIG_DM_BUS] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10reset: Add Raspberry Pi 4 firmware reset controllerNicolas Saenz Julienne
Raspberry Pi 4's co-processor controls some of the board's HW initialization process, but it's up to Linux to trigger it when relevant. Introduce a reset controller capable of interfacing with RPi4's co-processor that models these firmware initialization routines as reset lines. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10pci: Add driver for Broadcom BCM2711 SoC PCIe controllerSylwester Nawrocki
This patch adds basic driver PCI Express controller found on Broadcom set-top-box SoCs, e.g. BCM2711. The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI handling removed. The inbound access memory region is not currently parsed from dma-ranges DT property and a fixed 3GB region is used. The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 USB Host Controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10spi: kirkwood: Drop nondm codeBhargav Shah
Drop the nondm code from kirkwood_spi.c since there is no board or any other code using for it. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09dtoc: extend dtoc to use struct driver_info when linking nodesWalter Lozano
In the current implementation, when dtoc parses a dtb to generate a struct platdata it converts the information related to linked nodes as pointers to struct platdata of destination nodes. By doing this, it makes difficult to get pointer to udevices created based on these information. This patch extends dtoc to use struct driver_info when populating information about linked nodes, which makes it easier to later get the devices created. In this context, reimplement functions like clk_get_by_index_platdata() which made use of the previous approach. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09core: extend struct driver_info to point to deviceWalter Lozano
Currently when creating an U_BOOT_DEVICE entry a struct driver_info is declared, which contains the data needed to instantiate the device. However, the actual device is created at runtime and there is no proper way to get the device based on its struct driver_info. This patch extends struct driver_info adding a pointer to udevice which is populated during the bind process, allowing to generate a set of functions to get the device based on its struct driver_info. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09core: drop const for struct driver_infoWalter Lozano
In order to prepare for a new support of phandle when OF_PLATDATA is used drop the const for struct driver_info as this struct will need to be updated on runtime. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09core: add support for U_BOOT_DRIVER_ALIASWalter Lozano
Currently when using OF_PLATDATA the binding between devices and drivers is done trying to match the compatible string in the node with a driver name. However, usually a single driver supports multiple compatible strings which causes that only devices which its compatible string matches a driver name get bound. To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro, which generates no code at all, but allows an easy way to declare driver name aliases. Thanks to this, dtoc could be improve to look for the driver name based on its alias when it populates the U_BOOT_DEVICE entry. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09drivers: rename drivers to match compatible stringWalter Lozano
When using OF_PLATDATA, the bind process between devices and drivers is performed trying to match compatible string with driver names. However driver names are not strictly defined, and also there are different names used when declaring a driver with U_BOOT_DRIVER, the name of the symbol used in the linker list and the used in the struct driver_info. In order to make things a bit more clear, rename the drivers names. This will also help for further OF_PLATDATA improvements, such as checking for valid driver names. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour: Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-09sandbox: spi: sandbox_sf_state_name() is requiredHeinrich Schuchardt
Compiling drivers/mtd/spi/sandbox.c fails when compiled with CONFIG_LOG=n: In file included from include/common.h:20, from drivers/mtd/spi/sandbox.c:13: drivers/mtd/spi/sandbox.c:295:15: error: format ‘%s’ expects argument of type ‘char *’, but argument 7 has type ‘int’ [-Werror=format=] 295 | log_content(" cmd: transition to %s state\n", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’ 37 | #define pr_fmt(fmt) fmt | ^~~ include/log.h:128:30: note: in expansion of macro ‘log_nop’ 128 | #define log_content(_fmt...) log_nop(LOG_CATEGORY, \ | ^~~~~~~ drivers/mtd/spi/sandbox.c:295:3: note: in expansion of macro ‘log_content’ 295 | log_content(" cmd: transition to %s state\n", | ^~~~~~~~~~~ drivers/mtd/spi/sandbox.c:295:37: note: format string is defined here 295 | log_content(" cmd: transition to %s state\n", | ~^ | | | char * | %d Supply function sandbox_sf_state_name() independent of CONFIG_LOG. Fixes: c3aed5db591e ("sandbox: spi: Add more logging") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09mtd: spi-nor: Enable QE bit for ISSI flash in case of SFDPPragnesh Patel
Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>