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2019-07-19ram: rk3399: Order tsel variablesJagan Teki
Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_pJagan Teki
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_nJagan Teki
Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_pJagan Teki
Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_nJagan Teki
Rename tsel_wr_select_n to tsel_wr_select_dq_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Handle pctl_cfg return typeJagan Teki
Add proper return type handling of pctl_cfg with meaningful print statement. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/sdram_params/paramsJagan Teki
Rename variable name of struct rk3399_sdram_params from sdram_params with params for more code readability. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Some trivial code fixesJagan Teki
- Add proper spaces in data training, rk3399_dmc_init, pctl_cfg - Order include files - Move macro after include files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Fix code warningsJagan Teki
Fix checkpatch warninigs on sdram_rk3399.c like - Avoid CamelCase - Unnecessary parentheses - Alignment should match open parenthesis - multiple blank lines - misspelled - spaces preferred around that '>>' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: xhci: Remove RK3399 supportMark Kettenis
Remove RK3399 compatible strings as this driver is no longer used on that SoC. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19usb: xhci-dwc3: Add USB2 PHY configurationMark Kettenis
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19usb: dwc3-of-simple: Add support for RK3399Mark Kettenis
Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-18Merge branch '2019-07-17-master-imports'Tom Rini
- Various FS/disk related fixes with security implications. - Proper fix for the pci_ep test. - Assorted bugfixes - Some MediaTek updates. - 'env erase' support.
2019-07-18pci_ep: fix wrong addressing to barnoRamon Fried
barno was mistakely readed from the target structure, resulting in undefined behavious depending on the previous memory content. fix that. Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver") Signed-off-by: Ramon Fried <rfried.dev@gmail.com> [trini: Drop unused bar_idx] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-18blk: Invalidate block cache when switching hwpartWeijie Gao
Some storage devices have multiple hw partitions and both address from zero, for example eMMC. However currently block cache invalidation only applies to block write/erase. This can cause a problem that data of current hw partition is cached before switching to another hw partition. And the following read operation of the latter hw partition will get wrong data when reading from the addresses that have been cached previously. To solve this problem, invalidate block cache after a successful select_hwpart operation. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18regulator: Allow enabling GPIO regulatorSven Schwermer
Drivers need to be able to enable regulators that may be implemented as GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is commonly implemented as a GPIO regulator in order to switch between I/O voltage levels. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18regulator: Factor out common enable codeSven Schwermer
In preparation of being able to enable/disable GPIO regulators, the code that will be shared among the two kinds to regulators is factored out into its own source files. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18rtc: Add DM support to ds3231Chuanhua Han
Add an implementation of the ds3231 driver that uses the driver model i2c APIs. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-17i2c: omap24xx_i2c: Adapt driver to support K3 devicesVignesh R
K3 devices have I2C IP that is same as OMAP2+ family. Allow driver to be compiled for ARCH_K3. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-17mmc: am654_sdhci: Allow driver to probe without PDs specifiedAndreas Dannenberg
We would like to use the driver even without power domains being specified for cases such as during early boot when the required power domains have already gotten enabled by the SoC's boot ROM and such explicit initialization is not needed and possible. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Add a platform specific set_control_reg() callbackFaiz Abbas
Add a platform specific set_control_reg() callback to help switch to UHS speed modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timingsFaiz Abbas
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific to arasan/zynq controllers. Add the same to sdhci.h. Also create a common API to set UHS timings in HOST_CONTROL2. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Add Support for PHYFaiz Abbas
Add support in the driver for handling phy specific registers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Make set_ios_post() return intFaiz Abbas
Make set_ios_post() return int to faciliate error handling in platform drivers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-17mmc: sdhci: Make sdhci_set_clock() non staticFaiz Abbas
The am654_sdhci driver needs to switch the clock off before disabling its phy dll and needs to re-enable the clock before enabling the phy again. Therefore, make the sdhci_set_clock() function accessible in the am654_sdhci driver. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Add support for sdhci-caps-maskFaiz Abbas
Add Support for masking some bits in the capabilities register of a host controller. Also remove the redundant readl() into caps1. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17regmap: Add API regmap_init_mem_index()Faiz Abbas
In device nodes with more than one entry in the reg property, it is sometimes useful to regmap only of the entries. Add an API regmap_init_mem_index() to facilitate this. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Remove quirksFaiz Abbas
The host controller works perfectly well without having to add any quirks. Remove them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17arm64: dts: k3: Sync sdhci0 node from kernel and change driver nameFaiz Abbas
Sync the sdhci0 node from kernel. This changes the compatible that is required to be there in the driver. Change the same for the SD card node which is not yet supported in kernel. This also syncs the main_pmx0 node as a side effect. Also change the name of the driver to match the compatible in kernel. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-16Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
2019-07-16sunxi: phy: Add USB PHY support for Allwinner H6Andre Przywara
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara
To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: gpio: Enable support for H6 pin controllerAndre Przywara
The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: move SUNXI_GPIO to KconfigAndre Przywara
Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-15Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2019-07-15net: macb: Add support for 1000-baseXRadu Pirea
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: macb: Fixed reading MII_LPA registerRadu Pirea
If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driverKeerthy
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addrKeerthy
Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: cortina: Use block layer to read from mmcYinbo Zhu
This patch is to use block layer to read from mmc in cortina Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: mscc: refactor mscc_miimHoratiu Vultur
Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15test: dm: add MDIO testAlex Marginean
A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: introduce MDIO DM class for MDIO devicesAlex Marginean
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: mscc: serval: Remove delay when serdes is configuredHoratiu Vultur
When serdes configuration was written in hardware there was a delay of 100ms to be sure that configuration was written. But the delay is not needed because already the function serdes_write it is checking that the operation finished. Therefore remove the mdelay. This improves the speed of configuring the network driver. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: ti: Fix clock output DT propertyTrent Piepho
The code block reading the DT property for the clock output control was before the phy's DT node pointer was set, so it could never work. Move it after the node pointer is set. Also store the unsigned 32-bit property into an unsigned value, not a signed value, as the former will cause a problem if value overflows. For instance, if one were to add 0xffffffff as a code to mean the clock output should be turned off. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: ti: Use default values for tx/rx delay and fifo sizeTrent Piepho
When not using DM_ETH, these PHY settings are programmed with default values hardcoded into the driver. When using DM_ETH, they should come from the device tree. However, if the device tree does not have the properties, the driver will silent use -1. Which is entirely out of range, programs nonsense into the PHY's registers, and does not work. Change this to use the same defaults as non-DM_ETH if the device tree is lacking the properties. As an alternative, the kernel driver for the phy will display an error message and fail if the device tree is lacking. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15Merge tag 'mmc-2019-7-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- mmc spi driver model support - drop mmc_spi command - enhanced Strobe mmc HS400 support - minor mmc bug/fixes and optimization - omap hsmmc and mvbeu update - sdhci card detect support
2019-07-15mmc: fsl_esdhc_imx: enlarge mmc timeoutPeng Fan
Flash system partition with fastboot will earse the partition firstly The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make it works for most of sdcard Cc: guoyin.chen <guoyin.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: add i.MX8QM compatiblePeng Fan
Add i.MX8QM compatible and soc data, the soc data is following Linux i.MX SDHC driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit (git 2.34.1) at 2024-12-27 19:55:13 +0000