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The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Drop the ad-hoc DT caps parsing in favor of common framework function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Add Kconfig entry for the Renesas SDHI variant of the controller
and split the Makefile entries accordingly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Factor out common code from the uniphier SD driver, change the prefix
of the functions from uniphier_sd_ to matsu_sd_ and create separate
renesas-sdhi.c driver. Thus far, all the code is still compiled when
CONFIG_UNIPHIER_MMC is selected and there is no functional change.
This patch is a preparation for further split of the SoC specific
parts of the Matsushita SD driver, used both on Uniphier and R-Car.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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This patch fixes a situation where CONFIG_DM_SERIAL is enabled for
regular U-Boot and SPL, but not for TPL. In that case, the build
will try to include serial-uclass into the TPL nonetheless, because
CONFIG_DM_SERIAL is set.
The solution is to check if the build is for SPL or TPL and in that
case, check if CONFIG_$(SPL_TPL_)DM_SERIAL is also set. Only in that
case, include serial-uclass.c . If the build is for regular U-Boot,
CONFIG_BUILD is not set, so only check if CONFIG_DM_SERIAL is set
and if so, include serial-uclass.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
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The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs
and an USB3 PHY. This patch adds drivers for these for the standard generic
PHY interface and supports the power-on/off calls and set the Host mode by
default.
They are based on the excellent work from Martin Blumenstingl merged in linux.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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DWC3 Ips can have more than 1 PHY for USB2 and 1 PHY for USB3, add support
for a generic number of PHYs and adapt the code to handle a generic
number of PHYs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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This is a port of the dwc3-of-simple driver from Linux to enable/deassert
clock and resets of a simple DWC3 Controller HW glue.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Add an option to get the clock speed from the device tree, hence adding
compatibility with DM clock drivers.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
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Since bus translations are now fully supported, use a plain
"dev_read_addr" to get the device address from the device tree.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
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The fpgamap interface has been switched to a "single function + data
size" interface. Reflect this change in the IHS I2C driver.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
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The commit implement a gpio-based software deblocking. The code
extract I2C pins description from device tree, switch pins to GPIO
mode, toggle SCL until slave release SDA, send I2C stop and switch
I2C pins back to I2C mode.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
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This patch adds the bulk clock API tests for the sandbox test suite.
It's very similar to the main test but only uses the _bulk() API and
checks if the clocks are correctly enabled/disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This patch adds a "bulk" API to the clock API in order to get/enable/disable
/release a group of clocks associated with a device.
This bulk API will avoid adding a copy of the same code to manage
a group of clocks in drivers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This patch adds the bulk reset API tests for the sandbox test suite.
Unlike the main test, it also check the "other" reset signal using the bulk API
and checks if the resets are correctly asserted/deasserted.
To allow the bulk API to work, and avoid changing the DT, the number of resets
of the sandbox reset controller has been bumped to 101 for the "other" reset
line to be valid.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This patch adds a "bulk" API to the reset API in order to get/deassert/
assert/release a group of reset signals associated with a device.
This bulk API will avoid adding a copy of the same code to manage
a group of reset signals in drivers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The Amlogic Meson SoCs serial bindings were not written when serial
support was pushed into Linux and U-Boot.
A clean bindings document has been merged into Linux tree to correctly
handle the multiple clocks feeding the serial peripheral.
This update the U-Boot serial_meson driver with the new compatible
string for Amlogic Meson GX Socs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding
driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Xilinx changes for v2018.05-rc2
- Various DT changes and sync with mainline kernel
- Various defconfig updates
- Add SPL init for zcu102 revA
- Add new zynqmp boards zcu100/zcu104/zcu106/zcu111/zc12XX
and zc1751-dc3
- Net fixes - xlnx,phy-type
- 64bit axi ethernet support
- arasan: Fix nand write issue
- fpga fixes
- Maintainer file updates
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This patch reads phytype from property "xlnx,phy-type" instead
od simply looking for "phy-type". This is to be inline with
Linux and also fixes the issue of detecting it wrongly in
u-boot.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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This patch uses writeq() function to enable greater than 32 bit
addressing of axi-ethernet for the ZynqMP devices.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Xilfpga library expects the size of bitstream in a pointer
but currenly we are passing the size as a value. This patch
fixes this issue.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Latest xilfpga expects to set BIT5 of flags for nonsecure
bitsream and also expects length in bytes instead of words
This patch does the same.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
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This patch adds support for ZynqMP platform to print FPGA PCAP status
for "fpga status" command.
Signed-off-by: Nitin Jain <nitinj@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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New and old clk drivers are sharing IDs and descriptions.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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In order that we can use eth_env_* even when CONFIG_NET isn't set, move
these functions to environment code from net code.
This fixes failures such as:
board/ti/am335x/built-in.o: In function `board_late_init':
board/ti/am335x/board.c:752: undefined reference to `eth_env_set_enetaddr'
u-boot/board/ti/am335x/board.c:766: undefined reference to `eth_env_set_enetaddr'
which caters for use cases such as:
commit f411b5cca48f ("board: am335x: Always set eth/eth1addr environment
variable")
when Ethernet is required in Linux, but not U-Boot.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
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In order to compile the USB Ethernet gadget support we require that NET
is enabled, add that dependency here.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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This converts CONFIG_DRIVER_TI_CPSW to Kconfig
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Migrate the CONFIG_FSL_ESDHC option to Kconfig.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
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Migrate the CONFIG_TSEC_ENET option to Kconfig.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
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As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 7b0947787358c6b277431d6b76ce043d8bec641d.
Signed-off-by: Tom Rini <trini@konsulko.com>
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As we aren't quite able to convert some platforms with a very small size
limit in SPL yet, we need to revert this for now.
This reverts commit 37434db29be495ef41f204a97b8bf13b1418f97d.
Signed-off-by: Tom Rini <trini@konsulko.com>
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A debug string still has the old name of a function being called; update
it.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Fix Kconfig alignment which should be <tab><space><space>.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rx8025 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
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As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rs5c372 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
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As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the mx27rtc implementation of
rtc_reset() can be an empty stub function.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
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As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1374 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
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As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1307 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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