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2020-01-08clk: imx: add i.MX8MP clk driverPeng Fan
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08clk: imx: add imx_clk_mux2_flagsPeng Fan
Add imx_clk_mux2_flags which will be used by i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08power: Add new PMIC PCA9450 driverYe Li
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08ddr: imx8m: Add DRAM PLL to generate 1000Mhz outputPeng Fan
We will generate DRAM 4000MT/s as default for i.MX8MP. So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08mxc_ocotp: support i.MX8MPPeng Fan
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks and ctrl register bit definitions, so update to reflect that. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08pinctrl: imx8m: support i.MX8MPPeng Fan
Add i.MX8MP compatible to let the pinctrl driver could support i.MX8MP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08mpc83xx_clk: always treat MPC83XX_CLK_PCI as invalidRasmus Villemoes
The current mpc83xx_clk driver is broken for any board for which mpc83xx_has_pci() is true, i.e. anything not MPC8308: When is_clk_valid() reports that MPC83XX_CLK_PCI is valid, init_all_clks() proceeds to call init_single_clk(), but that doesn't know about either MPC83XX_CLK_PCI or has any handling of the TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence init_single_clk() ends up returning -EINVAL, and the whole board hangs in serial_init(). The quickest fix is to simply pretend that clock is invalid for all, since nobody can have been relying on it. Adding proper support seems to be a bit more involved than just handling TYPE_SCCR_ONOFF: - The power-on-reset value of SCCR[PCICM] is 0, so mpc83xx_clk_enable() would probably need to be tought to enable the clock. - The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2 depending on the CFG_CLKIN_DIV configuration input, but that can't be read from software, so to properly fill out ->speed[MPC83XX_CLK_PCI] I think one would need guidance from Kconfig or dtb. Partially fixes: 07d538d281 clk: Add MPC83xx clock driver Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Mario Six <mario.six@gdsys.cc>
2020-01-07dm: Add a debug message when devices are skipped pre-relocSean Anderson
This adds a message to lists_bind_fdt when it skips initializing a device pre-relocation. I've had a couple errors where a device didn't initialize properly because one of its dependencies was missing. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-07dm: devres: Add a new OFDATA phaseSimon Glass
Since the ofdata_to_platdata() method can allocate resources, add it as a new devres phase. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: devres: Use an enum for the allocation phaseSimon Glass
At present we only support two phases where devres can be used: bind and probe. This is handled with a boolean. We want to add a new phase (platdata), so change this to an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: devres: Add testsSimon Glass
The devres functionality has very few users in U-Boot, but it still should have tests. Add a few basic tests of the main functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: devres: Convert to use loggingSimon Glass
At present when CONFIG_DEBUG_DEVRES is enabled, U-Boot prints log messages to the console with every devres allocation/free event. This causes most tests to fail since the console output is not as expected. In particular this prevents us from adding a device to sandbox which uses devres in its bind method. Move devres over to use U-Boot's logging feature instead, and add a new category for devres. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: core: Add a new flag to track platform dataSimon Glass
We want to avoid allocating platform data twice. This could happen if device_probe() is called after device_ofdata_to_platdata() for the same device. Add a flag to track whether device_ofdata_to_platdata() has been called on a device. Check the flag to make sure it doesn't happen twice, and clear the flag when the data is freed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: core: Export a new function to read platdataSimon Glass
Add a new internal function, device_ofdata_to_platdata() to handle allocating private space associated with each device and reading the platform data from the device tree. Call this new function from device_probe(). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: core: Allocate parent data separate from probing parentSimon Glass
At present the parent is probed before the child's ofdata_to_platdata() method is called. Adjust the logic slightly so that probing parents is not done until afterwards. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: core: Move ofdata_to_platdata() call earlierSimon Glass
This method is supposed to extract platform data from the device tree. It should be done before the device itself is probed. Move it earlier in the device_probe() function. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: core: Don't clear active flag twice when probe() failsSimon Glass
Remove this duplicated code, since the 'fail' label does this immediately. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07aspeed: ast2500: Read clock ofdata in the correct methodSimon Glass
At present the clock driver reads its ofdata in the probe() method. This is not correct although it is often harmless. However in this case it causes a problem, something like this: - ast_get_scu() is called (from somewhere) to get the SCI address - this probes the clock - first sets up ofdata (which does nothing at present) - DM marks clock device as active - DM calls pinctrl - pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe() - ast_get_scu() probes the clock, but sees it already marked as probed - ast_get_scu() accesses the clock's private data, with scu as NULL - DM calls clock probe function ast2500_clk_probe() which reads scu By putting the read of scu into the correct method, scu is read as part of ofdata setup, and everything is OK. Note: This problem did not matter until now since DM always probed all parents before reading a child's ofdata. The fact that pinctrl is a child of clock seems to trigger this strange bug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-01-07pci: Print a warning if the bus is accessed before probingSimon Glass
It is not possible to access a device on a PCI bus that has not yet been probed, since the bus number is not known. Add a warning to catch this error. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07usb: Drop use of BUG_ON() and WARN_ON()Simon Glass
These macros use __FILE__ which inserts the full path of the object file into U-Boot, thus increasing file size. Drop these usages. An older version of this patch was submitted here: http://patchwork.ozlabs.org/patch/1205784/ Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07dm: core: Use assert_noisy() in devresSimon Glass
Use this macros instead of the linux ones, as the output is smaller. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07virtio: rng: Add a random number generator(rng) driverSughosh Ganu
Add a driver for the virtio-rng device on the qemu platform. The device uses pci as a transport medium. The driver can be enabled with the following configs CONFIG_VIRTIO CONFIG_DM_RNG CONFIG_VIRTIO_PCI CONFIG_VIRTIO_RNG Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-01-07sandbox: rng: Add a random number generator(rng) driverSughosh Ganu
Add a sandbox driver for random number generation. Mostly aimed at providing a unit test for rng uclass. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07stm32mp1: rng: Add a driver for random number generator(rng) deviceSughosh Ganu
Add a driver for the rng device found on stm32mp1 platforms. The driver provides a routine for reading the random number seed from the hardware device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Remove a superfluous blank line Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-01-07clk: stm32mp1: Add a clock entry for RNG1 deviceSughosh Ganu
Add an entry for allowing clock enablement for the random number generator peripheral, RNG1. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07dm: rng: Add random number generator(rng) uclassSughosh Ganu
Add a uclass for reading a random number seed from a random number generator device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07power: regulator: support off-on-delay-usPeng Fan
off-on-delay-us has been supported by Linux, so let's use it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-07remoteproc: stm32: load resource table from firmwareFabien Dessenne
Load the optional resource table from the firmware, and write its address in the dedicated backup register. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07remoteproc: stm32: track the coprocessor state in a backup registerFabien Dessenne
Update the dedicated backup register to track the coprocessor state and rely on that register to compute the .is_running() value (which expects a return value of 0 -not 1- if the processor is running). Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07remoteproc: elf_loader: Add elf resource table load supportFabien Dessenne
Add rproc_elf_load_rsc_table(), which searches for a resource table in an elf64/elf32 image, and if found, copies it to device memory. Add also the elf32 and elf64 variants of this API. Add a test for this. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-07drivers: board: Add get_fit_loadable()Jean-Jacques Hiblot
This function will be used by the SPL to get the names of images to load from the FIT. This allows to load different images based on runtime HW detection. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07drivers: board: Make the board drivers available in SPLJean-Jacques Hiblot
Make the board driver available in the SPL too. The board driver is a way to provide useful information about the board and that can be useful in the SPL too. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07Merge tag 'u-boot-imx-20200107' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
2020-01-07Merge tag 'u-boot-atmel-2020.04-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.04 cycle This feature set is a patch series from Tudor Ambarus which includes parsing of the spi flash SFDP parser for SST flashes, and using those tables to retrieve unique saved per device MAC address. This is then used as base mac address on the SAMA5D2 Wireless SOM EK board.
2020-01-07ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer
The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07arm: socfpga: stratix10: Enable SMMU accessThor Thayer
Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan
Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07cache: Add Arteris Ncore cache coherent unit driverLey Foon Tan
Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert clock manager from struct to definesLey Foon Tan
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert reset manager from struct to definesLey Foon Tan
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07spl: Allow cache drivers to be used in SPLLey Foon Tan
Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07dfu: Add optional timeout parameterAndy Shevchenko
When the `dfu` command is called from the U-Boot environment, it now accepts an optional parameter that specifies a timeout (in seconds). If a DFU connection is not made within that time the `dfu` command exits (as it would if Ctrl+C was pressed). If the timeout is left empty or being zero the `dfu` command behaves as it does now. This is useful for allowing U-Boot to check to see if anything wants to upload new firmware before continuing to boot. The patch is based on the commit https://github.com/01org/edison-u-boot/commit/5e966ccc3c65c18c9783741fa04e0c45e021780c by Sebastien Colleur, which has been heavily reworked due to U-Boot changes in the past. Signed-off-by: Brad Campbell <bradjc5@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-07video: meson: Drop unnecessary header includesSimon Glass
These files should not be included in meson header files. Drop them and tidy up the affected C files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf
In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2020-01-07pci: imx: Add iMX6SX compatibleMarek Vasut
The driver works fine with iMX6SX, add the missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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