summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2019-07-29pinctrl: renesas: fix R-Car gpio0_00 operation fails with 'gpio -input' commandtitron
Fix GPIO bank 0 pin 0 request/release off by one error. Without this patch, it is not possible to request/release GPIO bank 0 pin 0. Signed-off-by: Tiezhuang Dong <tiezhuang.dong.yh@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-07-23pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2Eugeniu Rosca
In spite of the summary line, U-Boot commits [1-2] seem to have aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since they also imported the Linux 5.1 commits listed in [3]. What current commit tries to accomplish is to align the Gen2 and Gen3 pinctrl tables to Linux v5.2. Importing these updates in two steps as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult due to Linux commits like [5-6] which atomically update both Gen2/3 platforms and whose breakdown would not be easily possible. The detailed list of Linux commits squashed into this U-Boot patch is shown in [4]. The second column in [4] depicts the patch id mismatch between the original Linux and the resulted U-Boot commit. The exclamation mark means that manual conflict resolution was involved during cherry picking Linux commit into U-Boot repository (this is mainly caused by dropped changes in files like pfc-r8a7795-es1.c and pfc-r8a77980.c which are missing in U-Boot). This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and boot-tested on: - H3-ES2.0-Salvator-X - M3-ES1.1-Salvator-XS - M3N-ES1.1-ULCB [1] 8719ca81136474 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0") [2] a6a743df242a50 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0") [3] Linux 5.1 commits already contained in [1-2]: 79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions 729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions 16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions 86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3 b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups 81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions 08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions 99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions 85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins" f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability 5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering 3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering 7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2 699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0 [4] Linux 5.2 commits backported and squashed into this U-Boot patch Linux commit id Linux commit summary line 9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length 5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time 1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers 3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions 2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro 69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro 19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields 360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation 943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2 5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions 662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin 624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C} e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data 0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions [5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro") [6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-18Merge branch '2019-07-17-master-imports'Tom Rini
- Various FS/disk related fixes with security implications. - Proper fix for the pci_ep test. - Assorted bugfixes - Some MediaTek updates. - 'env erase' support.
2019-07-18pci_ep: fix wrong addressing to barnoRamon Fried
barno was mistakely readed from the target structure, resulting in undefined behavious depending on the previous memory content. fix that. Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver") Signed-off-by: Ramon Fried <rfried.dev@gmail.com> [trini: Drop unused bar_idx] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-18blk: Invalidate block cache when switching hwpartWeijie Gao
Some storage devices have multiple hw partitions and both address from zero, for example eMMC. However currently block cache invalidation only applies to block write/erase. This can cause a problem that data of current hw partition is cached before switching to another hw partition. And the following read operation of the latter hw partition will get wrong data when reading from the addresses that have been cached previously. To solve this problem, invalidate block cache after a successful select_hwpart operation. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18regulator: Allow enabling GPIO regulatorSven Schwermer
Drivers need to be able to enable regulators that may be implemented as GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is commonly implemented as a GPIO regulator in order to switch between I/O voltage levels. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18regulator: Factor out common enable codeSven Schwermer
In preparation of being able to enable/disable GPIO regulators, the code that will be shared among the two kinds to regulators is factored out into its own source files. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18rtc: Add DM support to ds3231Chuanhua Han
Add an implementation of the ds3231 driver that uses the driver model i2c APIs. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-17i2c: omap24xx_i2c: Adapt driver to support K3 devicesVignesh R
K3 devices have I2C IP that is same as OMAP2+ family. Allow driver to be compiled for ARCH_K3. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-17mmc: am654_sdhci: Allow driver to probe without PDs specifiedAndreas Dannenberg
We would like to use the driver even without power domains being specified for cases such as during early boot when the required power domains have already gotten enabled by the SoC's boot ROM and such explicit initialization is not needed and possible. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Add a platform specific set_control_reg() callbackFaiz Abbas
Add a platform specific set_control_reg() callback to help switch to UHS speed modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timingsFaiz Abbas
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific to arasan/zynq controllers. Add the same to sdhci.h. Also create a common API to set UHS timings in HOST_CONTROL2. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Add Support for PHYFaiz Abbas
Add support in the driver for handling phy specific registers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Make set_ios_post() return intFaiz Abbas
Make set_ios_post() return int to faciliate error handling in platform drivers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-17mmc: sdhci: Make sdhci_set_clock() non staticFaiz Abbas
The am654_sdhci driver needs to switch the clock off before disabling its phy dll and needs to re-enable the clock before enabling the phy again. Therefore, make the sdhci_set_clock() function accessible in the am654_sdhci driver. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Add support for sdhci-caps-maskFaiz Abbas
Add Support for masking some bits in the capabilities register of a host controller. Also remove the redundant readl() into caps1. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17regmap: Add API regmap_init_mem_index()Faiz Abbas
In device nodes with more than one entry in the reg property, it is sometimes useful to regmap only of the entries. Add an API regmap_init_mem_index() to facilitate this. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Remove quirksFaiz Abbas
The host controller works perfectly well without having to add any quirks. Remove them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17arm64: dts: k3: Sync sdhci0 node from kernel and change driver nameFaiz Abbas
Sync the sdhci0 node from kernel. This changes the compatible that is required to be there in the driver. Change the same for the SD card node which is not yet supported in kernel. This also syncs the main_pmx0 node as a side effect. Also change the name of the driver to match the compatible in kernel. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-16Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
2019-07-16sunxi: phy: Add USB PHY support for Allwinner H6Andre Przywara
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara
To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: gpio: Enable support for H6 pin controllerAndre Przywara
The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: move SUNXI_GPIO to KconfigAndre Przywara
Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-15Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2019-07-15net: macb: Add support for 1000-baseXRadu Pirea
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: macb: Fixed reading MII_LPA registerRadu Pirea
If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driverKeerthy
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addrKeerthy
Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: cortina: Use block layer to read from mmcYinbo Zhu
This patch is to use block layer to read from mmc in cortina Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: mscc: refactor mscc_miimHoratiu Vultur
Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15test: dm: add MDIO testAlex Marginean
A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: introduce MDIO DM class for MDIO devicesAlex Marginean
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: mscc: serval: Remove delay when serdes is configuredHoratiu Vultur
When serdes configuration was written in hardware there was a delay of 100ms to be sure that configuration was written. But the delay is not needed because already the function serdes_write it is checking that the operation finished. Therefore remove the mdelay. This improves the speed of configuring the network driver. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: ti: Fix clock output DT propertyTrent Piepho
The code block reading the DT property for the clock output control was before the phy's DT node pointer was set, so it could never work. Move it after the node pointer is set. Also store the unsigned 32-bit property into an unsigned value, not a signed value, as the former will cause a problem if value overflows. For instance, if one were to add 0xffffffff as a code to mean the clock output should be turned off. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: ti: Use default values for tx/rx delay and fifo sizeTrent Piepho
When not using DM_ETH, these PHY settings are programmed with default values hardcoded into the driver. When using DM_ETH, they should come from the device tree. However, if the device tree does not have the properties, the driver will silent use -1. Which is entirely out of range, programs nonsense into the PHY's registers, and does not work. Change this to use the same defaults as non-DM_ETH if the device tree is lacking the properties. As an alternative, the kernel driver for the phy will display an error message and fail if the device tree is lacking. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15Merge tag 'mmc-2019-7-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- mmc spi driver model support - drop mmc_spi command - enhanced Strobe mmc HS400 support - minor mmc bug/fixes and optimization - omap hsmmc and mvbeu update - sdhci card detect support
2019-07-15mmc: fsl_esdhc_imx: enlarge mmc timeoutPeng Fan
Flash system partition with fastboot will earse the partition firstly The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make it works for most of sdcard Cc: guoyin.chen <guoyin.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: add i.MX8QM compatiblePeng Fan
Add i.MX8QM compatible and soc data, the soc data is following Linux i.MX SDHC driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: add HS400 Enhanced strobe supportPeng Fan
Implement set_enhanced_strobe hook for fsl_esdhc_imx, ,in esdhc_set_timing and esdhc_change_pinstate, also handle HS400_ES. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: use mmc_of_parse to set host_capsPeng Fan
Use mmc_of_parse to set host_caps. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: Parse no-1-8-v DT propertyPeng Fan
Parse no-1-8-v DT Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-07-15mmc: Parse HS400 Enhanced strobe DT propertiesPeng Fan
Add HS400 Enhanced strobe properties parsing support to mmc_of_parse(). Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-07-15mmc: support hs400 enhanced strobe modePeng Fan
eMMC 5.1+ supports HS400 Enhances Strobe mode without the need for tuning procedure. The flow is as following: - set HS_TIMIMG (Highspeed) - Host change freq to <= 52Mhz - set the bus width to Enhanced strobe and DDR8Bit(CMD6), EXT_CSD[183] = 0x86 instead of 0x80 - set HS_TIMING to 0x3 (HS400) - Host change freq to <= 200Mhz - Host select HS400 enhanced strobe complete Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: fix config check issue when building in SPLYe Li
Should use CONFIG_IS_ENABLED not IS_ENABLED for clock and regulator drivers, CONFIG_IS_ENABLED will check the CONFIG_SPL_CLK and CONFIG_SPL_DM_REGULATOR when building SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15mmc: mmc_spi: Re-write driver using DM frameworkBhargav Shah
This patch rewrites MMC SPI driver using U-Boot DM framework and get it's working on SiFive Unleashed board. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15mmc: skip select_mode_and_width for MMC SPI hostAnup Patel
The MMC mode and width are fixed for MMC SPI host hence we skip sd_select_mode_and_width() and mmc_select_mode_and_width() for MMC SPI host. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15mmc: retry a few times if a partition switch failedJean-Jacques Hiblot
This operation may fail. Retry it a few times before giving up and report a failure. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15mmc: do not change mode when accessing a boot partitionJean-Jacques Hiblot
Accessing the boot partition had been error prone with HS200 and HS400 and was disabled. The driver first switched to a lesser mode and then switched the partition access. It was mostly due to a bad handling of the switch and has been fixed, so let's remove this 'feature' Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-07-15mmc: During a switch, poll on dat0 if available and check the final statusJean-Jacques Hiblot
The switch operation can sometimes make the bus unreliable, in that case the send_status parameter should be false to indicate not to poll using CMD13. If polling on dat0 is possible, we should use it to detect the end of the operation. At the end of the operation it is safe to use CMD13 to get the status of the card. It is important to do so because the operation may have failed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
generated by cgit (git 2.34.1) at 2025-02-05 13:42:56 +0000