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2019-07-20ram: rk3399: Configure phy IO in ds odtJagan Teki
Some dramtypes like lpddr4 initialization would required to configure phy IO even after pctl_cfg and after set_ds_odt. For those cases the set_ds_odt would be an initial call to setup the phy. To satisfy all the cases, trigger phy IO from set_ds_odt. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add DdrModeJagan Teki
Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddrtimingC0Jagan Teki
Add DdrTimingC0 structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add ddr version enc macroJagan Teki
Add dram config macro for handling ddr version number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Introduce sys_reg3 for more capacity infoJagan Teki
cs0_row, cs1_row and cs1_col needs more bits to show its correct value, update to make use of both sys_reg2, sys_reg3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash similar patches into one patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Rename sys_reg with sys_reg2Jagan Teki
Use dram config variable name as sys_reg2 instead of sys_reg since the final variable value is to written into a pmugrf register named as sys_reg2. This reflect the both variable and associated register names are same and also help to add next sys_reg's to add it in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Simply existing dram enc macroJagan Teki
Add simplified and meaningful macro for all setting. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (Squash the similar patches into 1 patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Enable sdram debug functionsJagan Teki
This would help to debug the sdram base parameters while debugging existing chip or while supporting new sdram type. It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG for showing the debug prints. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add rank detection supportJagan Teki
Right now the rk3399 sdram driver assume that the board has configured with 2 channels, so any possibility to enable single channel on the same driver will encounter channel #1 data training failure. Log: U-Boot TPL board init sdram_init: data training failed rk3399_dmc_init DRAM init failed -5 So, add an algorithm that can capable to compute the active or configured rank with associated channel like a) do rank loop to compute the active rank, with associated channel numbers b) then, succeed the data training only for configured channel c) preserve the rank for given channel d) do channel loop for setting the active channel e) if given rank is zero or inactive on the specific channel, clear the timings for the associated channel f) finally, return error if number of channels is zero Tested in NanoPI-NEO4 since it support single channel sdram configuration. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> (add PI_READ_GATE_TRAINING for LPDDR3 to support rk3399-evb case) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Compute stride for 1 channel aJagan Teki
Add stride computation for the sdram which support single channel a This configuration available in NanoPi NEO4 and the same can work with existing rk3399-sdram-ddr3-1866.dtsi Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Compute stride for 2 channelsJagan Teki
stride value from sdram timings can be computed dynamically based on the determined capacity for the given channel. Right now these stride values are taken as part of sdram timings via dtsi, but it possible to use same timings dtsi for given frequency even though the configured board sdram do support single channel with different size by dynamically detect the stride value. Example, NanoPi NEO4 do have DDR3-1866, but with single channel and 1GB size with dynamic stride detection it is possible to use existing rk3399-sdram-ddr3-1866.dtsi whose stride, number of channels and capacity it support is d efferent. So, add initial support to calculate the stride value for 2 channels sdram, which is available by default on existing boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: debug: Add sdram_print_strideJagan Teki
Add code to print the channel stride, this would help to print the stride of associated channel. Here is sample print on LPDDR4, 50MHz. 256B stride Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: debug: Get the cs capacityJagan Teki
Add code to get the channel capacity, this would help to print the capacity of specific channel. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: debug: Add sdram_print_ddr_infoJagan Teki
Add sdram ddr info print support, this would help to observe the sdram base parameters. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: Add debug sdram driverJagan Teki
Add sdram driver to handle debug across rockchip SoCs. This would help to improve code debugging feature for sdram drivers in rockchip family, whoever wants to debug the driver should call these core debug code on their respective platform sdram drivers. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: Add initial KconfigJagan Teki
Right now sdram drivers in rockchip SoC are built based on the SoC configs which may not be an adequate solutions while adding common or debug driver. So, add meaningful Kconfig options start with rk3399. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Add pctl start supportJagan Teki
Add support for pctl start for both channel 0, 1 control and phy registers. This would also handle pwrup_srefresh_exit init based on the channel number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Move pwrup_srefresh_exit to dram_infoJagan Teki
Add pwrup_srefresh_exit to be part of dram_info so-that the it can help to support pwrup_srefresh_exit in individual channels while starting pctl in future. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Add phy pctrl reset supportJagan Teki
Add support for phy pctrl reset support for both channel 0, 1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Use rank mask in wdql data trainingJagan Teki
Add rank_mask based on the rank number, this would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Use rank mask in ca data trainingJagan Teki
Add rank_mask based on the rank number, this would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Clear PI_175 interrupts in data trainingJagan Teki
Clear the PI_175 interrupts before processing actual data training in all relevant calls. This would help to clear interrupt from previous training. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Handle data training return typesJagan Teki
data trainings calls like ca, wl, rg, rl, wdql have proper return types with -EIO and the return type missed to handle in data_training function. This patch, add proper return type checks along with useful debug statement on each data training calls. Incidentally this would help to prevent the sdram initialization hang for single channel dram and when the code is trying to initialize second channel with proper return type of relevant data training call might failed. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: rockchip: rk3399: Fix check patch warnings and checksJagan Teki
- CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: rk3399: Add cap_info structureJagan Teki
Group common ddr attributes like - rank - col - bk - bw - dbw - row_3_4 - cs0_row - cs1_row - ddrconfig into a common cap_info structure for more code readability and extend if possible based on the new features. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Order tsel variablesJagan Teki
Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_pJagan Teki
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_nJagan Teki
Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_pJagan Teki
Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_nJagan Teki
Rename tsel_wr_select_n to tsel_wr_select_dq_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Handle pctl_cfg return typeJagan Teki
Add proper return type handling of pctl_cfg with meaningful print statement. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/sdram_params/paramsJagan Teki
Rename variable name of struct rk3399_sdram_params from sdram_params with params for more code readability. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Some trivial code fixesJagan Teki
- Add proper spaces in data training, rk3399_dmc_init, pctl_cfg - Order include files - Move macro after include files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Fix code warningsJagan Teki
Fix checkpatch warninigs on sdram_rk3399.c like - Avoid CamelCase - Unnecessary parentheses - Alignment should match open parenthesis - multiple blank lines - misspelled - spaces preferred around that '>>' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: xhci: Remove RK3399 supportMark Kettenis
Remove RK3399 compatible strings as this driver is no longer used on that SoC. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19usb: xhci-dwc3: Add USB2 PHY configurationMark Kettenis
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19usb: dwc3-of-simple: Add support for RK3399Mark Kettenis
Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-18Merge branch '2019-07-17-master-imports'Tom Rini
- Various FS/disk related fixes with security implications. - Proper fix for the pci_ep test. - Assorted bugfixes - Some MediaTek updates. - 'env erase' support.
2019-07-18pci_ep: fix wrong addressing to barnoRamon Fried
barno was mistakely readed from the target structure, resulting in undefined behavious depending on the previous memory content. fix that. Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver") Signed-off-by: Ramon Fried <rfried.dev@gmail.com> [trini: Drop unused bar_idx] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-18blk: Invalidate block cache when switching hwpartWeijie Gao
Some storage devices have multiple hw partitions and both address from zero, for example eMMC. However currently block cache invalidation only applies to block write/erase. This can cause a problem that data of current hw partition is cached before switching to another hw partition. And the following read operation of the latter hw partition will get wrong data when reading from the addresses that have been cached previously. To solve this problem, invalidate block cache after a successful select_hwpart operation. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18regulator: Allow enabling GPIO regulatorSven Schwermer
Drivers need to be able to enable regulators that may be implemented as GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is commonly implemented as a GPIO regulator in order to switch between I/O voltage levels. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18regulator: Factor out common enable codeSven Schwermer
In preparation of being able to enable/disable GPIO regulators, the code that will be shared among the two kinds to regulators is factored out into its own source files. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-18rtc: Add DM support to ds3231Chuanhua Han
Add an implementation of the ds3231 driver that uses the driver model i2c APIs. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-07-17i2c: omap24xx_i2c: Adapt driver to support K3 devicesVignesh R
K3 devices have I2C IP that is same as OMAP2+ family. Allow driver to be compiled for ARCH_K3. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-17mmc: am654_sdhci: Allow driver to probe without PDs specifiedAndreas Dannenberg
We would like to use the driver even without power domains being specified for cases such as during early boot when the required power domains have already gotten enabled by the SoC's boot ROM and such explicit initialization is not needed and possible. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Add a platform specific set_control_reg() callbackFaiz Abbas
Add a platform specific set_control_reg() callback to help switch to UHS speed modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timingsFaiz Abbas
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific to arasan/zynq controllers. Add the same to sdhci.h. Also create a common API to set UHS timings in HOST_CONTROL2. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Add Support for PHYFaiz Abbas
Add support in the driver for handling phy specific registers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Make set_ios_post() return intFaiz Abbas
Make set_ios_post() return int to faciliate error handling in platform drivers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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