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2019-03-08Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini
This pull request contains bugfixes for rcar_i2c, rcar_ii2c and i2c_cdns driver. Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek is a bugfix for arm64 builds, as discussed with Marek on list.
2019-03-08i2c: rcar_i2c: Move FSDA check to rcar_i2c_recoverIsmael Luceno Cortes
Cosmetic change. Any call to the recover function would need to do the same check afterwards, so it's sensible to make it part of the function. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
2019-03-08i2c: rcar_i2c: Set the slave address from rcar_i2c_xferIsmael Luceno Cortes
It needs to be done for both reads and writes, so do it at rcar_i2c_xfer to avoid duplication. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08i2c: rcar_i2c: Don't mask errors with EREMOTEIO at rcar_i2c_xferIsmael Luceno Cortes
Fix rcar_i2c_xfer return value, previously it was always returning -EREMOTEIO when dealing with errors from calls to the read/write functions. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08i2c: rcar_i2c: Fix sending of slave addressesIsmael Luceno Cortes
Do the reset before clearing the MSR, otherwise it may result in a read or write operation instead if the start condition is repeated. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08i2c: rcar_i2c: Add comments about registers & valuesIsmael Luceno Cortes
Document the meaning of macros related to registers and values to be written to them. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08i2c: rcar_i2c: Setup SCL/SDA delay at rcar_i2c_set_speedIsmael Luceno Cortes
Setting up the delay only needs to be done once; move it to rcar_i2c_set_speed so it's done at initialization time. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08i2c: i2c_cdns: Add support for handling arbitration lostSiva Durga Prasad Paladugu
This patch adds support for handling arbitration lost in case of multi master mode. When an arbitration lost is detected, it retries for 10 times before failing. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08i2c: i2c_cdns: Fix clearing of all interruptsSiva Durga Prasad Paladugu
The arbitration lost interrupt was not getting cleared while clearing interrupts. This patch fixes this by adding arbitration lost interrupt as well during clear. This patch also removes hardcoded value and defined a macro for it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-07i2c: rcar_i2c: Add Gen3 SoC supportMarek Vasut
Add support for R-Car Gen3 SoCs into the driver, which encompases the Gen3 SoC extra timing register handling and 64bit build fixes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-07i2c: rcar_iic: Read ICSR only onceMarek Vasut
Read ICSR only once to avoid missing interrupts. This happens on R8A7791 Porter during reset, when reading the PMIC register 0x13, which may fail sometimes because of the missed DTE interrupt. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-06Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
- dw spi include file fix - Allwinner A31 spi, been in ML in many releases.
2019-03-04Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Assorted PFC fixes
2019-03-04spi: Rename sun4i_spi.c into spi-sunxi.cJagan Teki
Now the same SPI controller driver is reusable in all Allwinner SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c which eventually look like a common sunxi driver. Also update the function, variable, structure names in driver from sun4i into sunxi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4i: Driver cleanupJagan Teki
- drop unused macros. - use base instead of base_addr, for better code readability - move .probe and .ofdata_to_platdata functions in required places to add platdata support in future. - use sentinel sun4i_spi_ids. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4: Add A31 spi controller supportJagan Teki
The usual SPI transmission protocol in Allwinner A10 and A31 controllers share similar context with minimal changes in register offsets along with few additional register bits on A31. So, add A31 spi controller support in existing sun4i_spi with A31 specific register offsets and bits. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04spi: sun4i: Add CLK supportJagan Teki
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver. Clock disablement could be done while releasing the bus transfer, but the existing code doesn't disable the clocks it only taken care of clock enablement globally in probe. So to make a proper clock handling, the clocks should enable it in claim and disable it in release. This patch would also do that change, by enable and disable clock in proper order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: sun4i: Support fifo_depth via drvdataJagan Teki
Support fifo_depth via drvdata instead of macro definition, this would eventually reduce another macro definition for new SPI controller fifo depth support addition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: sun4i: Access registers and bits via enum offsetsJagan Teki
Allwinner support two different SPI controllers one for A10 and another for A31 with minimal changes in register offsets and respective register bits, but the logic for accessing the SPI master via SPI slave remains nearly similar. Add enum offsets for register set and register bits, so-that it can access both classes of SPI controllers. Assign same control register for global, transfer and fifo control registers to make the same code compatible with A31 SPI controller. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
2019-03-04spi: sun4i: Simplify reg writes using set/clrbits_le32Jagan Teki
Update the existing register writes using setbits_le32 and clrbits_le32 in required places. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04clk: sunxi: Implement SPI clocks, resetsJagan Teki
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: sun4i: Poll for rxfifo to be filled upJagan Teki
To drain rx fifo the fifo need to poll for how much data has been filled up in rx fifo. To achieve this, the current code is using wait_for_bit logic on control register with exchange burst mode mask, which is not a proper way of waiting for fifo filled up. So, add code for polling rxfifo to be filled up using fifo status register. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04spi: designware: Change include orderHoratiu.Vultur@microchip.com
With current order of include files, the file designware_spi.c can't see that the struct global_data has the member board_type when CONFIG_BOARD_TYPES is defined. By not seeing this then all the members are shifted in the struct global_data. So when the driver is trying to read from device tree blob, it would pass the wrong address to the function 'fdtdev_get_int'. This will make to use the default frequency 500000. The fix consists of changing the order of include files in designware_spi.c to include first common.h file. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-03-04pinctrl: renesas: r8a77990: Reivse USB ID pin nameHiroyuki Yokoyama
Since the datasheet Rev.1.00 has an error about the USB ID pin name, this patch revises it. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0Hiroyuki Yokoyama
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50, the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected, and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is selected. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_NHiroyuki Yokoyama
According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0 bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are selected. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit2 when using RX2,TX2 and SCK2Hiroyuki Yokoyama
According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0 bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are selected. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: r8a77990: Fix rename RTSx_N_TANS_x to RTSx_N_xHiroyuki Yokoyama
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR / MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndfHiroyuki Yokoyama
This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22] of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Remove r8a779{5,6,65} CC5_OSCOUT of IP17Hiroyuki Yokoyama
This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795 / r8a7796 / r8a77965. This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Fix r8a779{5,6,65} rename sel_adg_ to sel_adgHiroyuki Yokoyama
This patch fixes to the correct names, and "_" is not include after "adg" for r8a7795/r8a7796/r8a77965. This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04pinctrl: renesas: Fix r8a779{5,6,65} assign to GP7_03/02 of GPSR7Hiroyuki Yokoyama
This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03", and "HDMI0_CEC" to "GP7_02". This information was confirmed in the R-Car Gen3 Hardware Manual Rev.1.50. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-03configs: fsl: move DDR specific defines to KconfigRajesh Bhagat
Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- SoCFPGA cache/gpio fixes
2019-02-28Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Gen2/Gen3 fixes for warnings and sdhi
2019-02-28spi: omap3: fix set_wordlen() reading from incorrect address for CHCONFDavid Rivshin
_omap3_spi_set_wordlen() indexed the regs->channel[] array with the old wordlen (instead of the chipselect number) when reading the current CHCONF register value. This meant it read from the wrong memory location, modified that value, and then wrote it back to the correct CHCONF register. The end result is that most slave configuration settings would be lost, such as clock divisor, clock/chipselect polarities, etc. Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin <drivshin@allworx.com>
2019-02-27cpu: Bind timer driver for boot hartAtish Patra
Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27drivers: serial_sifive: Skip baudrate config if no input clockAtish Patra
It is possible that input clock is not available because clk device was not available and 'clock-frequency' DT property is also not available. In this case, instead of failing we should just skip baudrate config by returning zero. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-27drivers: serial_sifive: Fix baud rate calculationAtish Patra
Compute the baud rate multipler with more precision. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-02-27clk: Add fixed-factor clock driverAnup Patel
This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27clk: Add SiFive FU540 PRCI clock driverAnup Patel
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-27net: macb: Fix GEM hardware detectionAtish Patra
Fix MID bit field check to correctly identify all GEM hardwares. The check is updated as per macb driver in Linux location: <linux_sources>/drivers/net/ethernet/cadence/macb_main.c:259 Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27net: macb: Fix clk API usage for RISC-V systemsAnup Patel
Don't fail in macb_enable_clk() if clk_enable() returns -ENOSYS because we get -ENOSYS for fixed-rate clocks. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8Marek Vasut
According to latest specification rev.0026 and after confirmation with HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on H3 ES2.0 SoC. Make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25mmc: tmio: Clear BUSWIDTH bit when WMODE bit is setMarek Vasut
According to latest specification rev.0026, when HOST_MODE bit 0 (WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear HOST_MODE bit 8 in such case and align the code with Linux and avoid possible unforeseen issues. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-25pinctrl: renesas: Drop def_bool per SoCMarek Vasut
Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25clk: rmobile: Drop def_bool per SoCMarek Vasut
Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25gpio: altera_pio: fix get_valueJulien Béraud
gpio_get_value should return 0 or 1, not the value of bit & (1 << pin) Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
2019-02-20Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2019-02-20Merge git://git.denx.de/u-boot-x86Tom Rini
- Add support for sound. Albeit the big changeset, changes are pretty limited to x86 only and a few new sound drivers used by x86 so I think it would be good to have this in the next release.
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