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2020-01-20dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfersVignesh Raghavendra
Fix up the debug prints that were dumping state of TCHAN RT registers to use tchan for MEM_TO_DEV transfers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Remove coherency check for cache opsVignesh Raghavendra
Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandleVignesh Raghavendra
Instead of looking getting reference to SYSFW device using name which is not guaranteed to be constant, use phandle supplied in the DT node to get reference to SYSFW Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/popVignesh Raghavendra
Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20dma: ti: k3-udma: Query DMA channels allocated from Resource ManagerVignesh Raghavendra
On K3 SoCs, DMA channels are shared across multiple entities, therefore U-Boot DMA driver needs to query resource range from centralised resource management controller i.e SystemFirmware and use DMA channels allocated for A72 host. Add support for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20thermal: ti-bandgap: Fix adc value datatypeFaiz Abbas
The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to be indexed into a lookup table to get the actual temperature. Fix the naming and datatype of the adc value variable. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-17common: Move hang() to the same header as panic()Simon Glass
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Rename and move source()Simon Glass
This function has a very generic name which does not adequately describe its purpose. Rename it and move it to image.h, since it relates to reading a script from an image. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move the image globals into image.hSimon Glass
These three globals relate to image handling. Move them to the image header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17image: Rename load_addr, save_addr, save_sizeSimon Glass
These global variables are quite short and generic. In fact the same name is more often used locally for struct members and function arguments. Add a image_ prefix to make them easier to distinguish. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move reset_cpu() to the CPU headerSimon Glass
Move this function out of common.h and into a relevant header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move get_tbclk() to time.hSimon Glass
This function related to timer and most of the timer functions are in time.h, so move this function there. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move clock functions into a new fileSimon Glass
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Move ll_boot_init() to init.hSimon Glass
This is an init-related function so belongs in that file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17common: Drop floppy disk supportSimon Glass
This seems pretty old now. It has not been converted to driver model and is not used by any boards. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-16Merge tag 'mmc-1-16-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- Cleanup of fsl_esdhc driver together with arch/defconfig change - Add quirk for APP_CMD retry
2020-01-16Merge tag 'xilinx-for-v2020.04' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.04 ARM64: - Add INIT_SPL_RELATIVE dependency SPL: - FIT image fix - Enable customization of bl2_plat_get_bl31_params() Pytest: - Add test for octal/hex conversions Microblaze: - Fix manual relocation for one SPI instance Nand: - Convert zynq/zynqmp drivers to DM Xilinx: - Enable boot script location via Kconfig - Support OF_SEPARATE in board FDT selection - Remove low level uart setup it is done later by code - Add support for DEVICE_TREE variable passing for SPL Zynq: - Enable jtag boot mode via distro boot - Removing unused baseaddresses from hardware.h - DT fixups ZynqMP: - Fix emmc boot sequence - Simplify spl logic around bss and board_init_r() - Support psu_post_config_data() calling - Tune mini-nand DTS - Fix psu wiring for a2197 boards - Add runtime MMC device boot order filling in spl - Clear ATF handoff handling with custom bl2_plat_get_bl31_params() - Add support u-boot.its generation - Use single image configuration for all platforms - Enable PANIC_HANG via Kconfig - DT fixups - Firmware fixes - Add support for zcu208 and zcu1285 Versal: - Fix emmc boot sequence - Enable board_late_init() by default
2020-01-16mmc: add mmc and sd support for MT7622Sam Shih
This patch add mmc and sd support for Mediatek MT7622 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16power: domain: add power domain support for MT7622Sam Shih
This patch add power domain support for Mediatek MT7622 SoCs Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16clk: mediatek: fix clock-rate overflow problemSam Shih
This patch fix clock-rate overflow problem in mediatek clock driver common part. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: add driver for MT7622Sam Shih
This patch add clock driver for MediaTek MT7622 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16pinctrl: mediatek: add support for different pinctrlSam Shih
Due to the pinctrl hardware of MT7622 is difference from others SoC which using the common part of mediatek pinctrl. So we need to modify the common part of mediatek pinctrl. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16pinctrl: mediatek: add driver for MT7622Sam Shih
This patch add Pinctrl driver for MediaTek MT7622 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: make ref clock optionalChunfeng Yun
If make the ref clock optional, no need refer to fixed-clock when the ref clock is always on or comes from oscillator directly. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16phy: phy-mtk-tphy: remove the check of -ENOSYSChunfeng Yun
No need check -ENOSYS anymore after add dummy_enable() for fixed-clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fixed_rate: add dummy enable() functionChunfeng Yun
This is used to avoid clk_enable() return -ENOSYS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: add APIs to get (optional) clock by name without a deviceChunfeng Yun
Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: check valid clock by clk_valid()Chunfeng Yun
Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: fix error check for devm_clk_get_optional()Chunfeng Yun
If skip all return error number, it may skip some real error cases, so only skip the error when the clock is not provided in DTS Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16clk: mediatek: mt7629: add support for ssusbsysChunfeng Yun
The SSUSB IP's clocks come from ssusbsys module on mt7629, so add its driver Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16mmc: mtk-sd: fix hang when data read quicklymingming lee
For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCsmingming lee
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs. MT8512/MT8110 SoCs puts the tune register at top layer, so need add new code to support it. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16pinctrl: mediatek: add driver for MT8512mingming lee
Add Pinctrl driver for MediaTek MT8512 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pllmingming lee
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
2020-01-16clk: mediatek: add set_clr_upd mux type flowmingming lee
Add new set_clr_upd mux type and related operation to mtk common clock driver to support mt8512
2020-01-16clk: mediatek: add driver support for MT8512mingming lee
Add clock driver for MediaTek MT8512 SoC, include topckgen, apmixedsys and infracfg support. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16mmc: config help typo fixJoel Johnson
Fix typo in description of MMC_QUIRKS config option. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
2020-01-16mmc: add additional quirk for APP_CMD retryJoel Johnson
It was observed (on ClearFog Base) that sending MMC APP_CMD returned an error on the first attempt. The issue appears to be timing related since even inserting a puts() short debug entry before the execution added sufficient delay to receive success on first attempt. Follow the existing quirks pattern to retry if initial issuance failed so as to not introduce any delay unless needed. Signed-off-by: Joel Johnson <mrjoel@lixil.net>
2020-01-16Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu
The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16mmc: fsl_esdhc: drop useless fdt fixupYangbo Lu
The fdt fixup for properties "peripheral-frequency" and "adapter-type" was once for a Freescale SDK release. The properties haven't been existed in linux mainline. Drop these useless code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock codeYangbo Lu
Drop QorIQ eSDHC specific peripheral clock code. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-15Add dependencies for MALLOC_F and OF_LIBFDTSean Anderson
Some features implicitly depended on MALLOC_F and OF_LIBFDT and would fail at link-time if these features were not enabled. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-15Kconfig: Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMAVignesh Raghavendra
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use macros such as CONFIG_IS_ENABLED() that allow conditional compilation of code for SPL and U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-14mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhcGiulio Benetti
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms with CONFIG_DM_MMC=y. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statementGiulio Benetti
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK instead. So building could result in failure due to missing mxc_get_clock(). Make if(CONFIG_IS_ENABLED(CLK)) an #if statement. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14ram: add SDRAM driver for i.MXRT SoCsGiulio Benetti
Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14serial_lpuart: add support for i.MXRTGiulio Benetti
Add i.MXRT compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations. Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 as done for i.MX8. It needs also to set baudrate the same way as i.MX8 does. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14serial_lpuart: add clock enable if CONFIG_CLK is definedGiulio Benetti
This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined. If clock is not found, because DM is not used, let's emit a warning and proceed, because serial clock could also be already enabled by non DM code. If clock is found but cna't be enabled then return with error. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14gpio: mxc_gpio: add support for i.MXRT1050Giulio Benetti
Add i.MXRT1050 support, there are 5 GPIO banks. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
generated by cgit (git 2.34.1) at 2024-12-28 14:22:39 +0000