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2019-11-04Merge branch '2019-11-04-ti-imports'Tom Rini
- Various CPSW related improvements, DTS resync
2019-11-04net: ti: cpsw: convert to use dev/ofnode apiGrygorii Strashko
Conver TI CPSW driver to use dev/ofnode api. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> [trini: Add <dm/ofnode.h> to provide the prototype to ofnode] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-03Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Add support for Intel FSP-S and FSP-T in binman - Correct priority selection for image loaders for SPL - Add a size check for TPL - Various small SPL/TPL bug fixes and changes - SPI: Add support for memory-mapped flash
2019-11-03nand: mxs_nand: add API for switching different BCH layoutsIgor Opaniuk
On i.MX7 in a sake of reducing the disturbances caused by a neighboring cells in the FCB page in the NAND chip, a randomizer is enabled when reading the FCB page by ROM bootloader. Add API for setting BCH to specific layout (and restoring it back) used by ROM bootloader to be able to burn it in a proper way to NAND using nandbcb command. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee> Tested-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03mach-imx: Adding new argument for SIP call interfaceYe Li
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ, so update the interface to add new argument. Signed-off-by: Ye Li <ye.li@nxp.com> [agust: fixed imx8m-power-domain build] Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03power: pmic: Kconfig: add CONFIG_SPL_DM_PMIC_BD71837Peng Fan
Add CONFIG_SPL_DM_PMIC_BD71837 to make this driver could be used in SPL stage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03pmic: bd71837: drop DEBUG macroPeng Fan
Drop DEBUG macro definition which is used for debug purpose. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03video: mxsfb: set gd->fb_baseSébastien Szymanski
Set gd->fb_base so it can be shown with bdinfo command. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03watchdog: imx: Use immediate reset bits for expire_nowRobert Hancock
The expire_now function was previously setting the watchdog timeout to minimum and waiting for the watchdog to expire. However, this watchdog also has bits to trigger immediate reset. Use those instead, like the Linux imx2_wdt driver does. Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03watchdog: imx: Add DT ext-reset handlingRobert Hancock
The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the device tree to specify whether the board design should use the external reset instead of the internal reset. Use this boolean to determine which mode to use rather than using external reset unconditionally. For the legacy non-DM mode, the external reset is always used in order to maintain the previous behavior. Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid modeGrygorii Strashko
Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping default value (enabled) for MAC TX internal delay when "rgmii-rxid" interface mode is selected. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: fix mac tx internal delay for rgmii-rxid modeGrygorii Strashko
Now TI CPSW driver will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping default value (enabled) for MAC TX internal delay when "rgmii-rxid" interface mode is selected. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: add support for standard eth "max-speed" dt propertyGrygorii Strashko
This patch adds support for standard Ethernet "max-speed" DT property to allow PHY link speed limitation. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: move parsing of dt port's parameters in separate funcGrygorii Strashko
Move parsing of dt port's parameters in separate func for better code readability. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03net: ti: cpsw: enable 10Mbps link speed support in rgmii modeGrygorii Strashko
According to TRMs the 10Mbps link speed is supported in RGMII only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_SL_MACCTRL.EXT_EN(18) = 1. Hence update cpsw_slave_update_link() to follow documentation. [1] https://patchwork.kernel.org/patch/10285239/ Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03x86: timer: Use a separate flag for whether timer is initedSimon Glass
At present the value of the timer base is used to determine whether the timer has been set up or not. It is true that the timer is essentially never exactly 0 when it is read. However 'time 0' may indicate the time that the machine was reset so it is useful to be able to denote that. Update the code to use a separate flag instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: timer: Set up the timer in timer_early_get_count()Simon Glass
This function can be called before the timer is set up. Make sure that the init function is called so that it works correctly. This is needed so that bootstage can work correctly in TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03spi: Add support for memory-mapped flashSimon Glass
On x86 platforms the SPI flash can be mapped into memory so that the contents can be read with normal memory accesses. Add a new SPI method to find the location of the SPI flash in memory. This differs from the existing device-tree "memory-map" mechanism in that the location can be discovered at run-time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-01Merge tag 'arc-fixes-for-2020.01-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-arc ARC fixes for v2020.01-rc2 The main change is move to DM_MMC of yet 2 another ARC boards: AXS101 & IoTDK. Among that we improve handling of stock-formatted SD-cards of high volume on EM SDP as well as introduction of reset driver for HSDK which is required for prepser reinitialization of some peripherals like USB etc.
2019-11-01ARC: HSDK: introduce reset driverEugeniy Paltsev
Introduce reset driver for Synopsys ARC HSDK SoC Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-01Merge tag 'efi-2020-01-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-01-rc2 Provide a better user interface for setting UEFI variables. Bug fixes: - ext4 file system not discovered on UEFI block device - 'make tests' build error on 32bit systems
2019-11-01Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dmTom Rini
- Fix for patman with email addresses containing commas - Bootstage improvements for TPL, SPL - Various sandbox and dm improvements and fixes
2019-10-31drivers: phy: Handle gracefully NULL pointersJean-Jacques Hiblot
For some controllers PHYs can be optional. Handling NULL pointers without crashing nor failing, makes it easy to handle optional PHYs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-31ata: ahci allow 64-bit DMA for SATARoman Kapl
Allow 64-bit DMA on AHCI. If not supported by the host controller, at least print a message and fail. Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-10-31nvme: use page-aligned buffer for identify commandPatrick Wildt
Change the stack-allocated buffer for the identification command to explicitly allocate page-aligned buffers. Even though the spec seems to allow having admin queue commands on non page-aligned buffers, it seems to not be possible on my i.MX8MQ board with a a Silicon Power P34A80. Since all of the NVMe drivers I have seen always do admin commands on a page-aligned buffer, which does work on my system, it makes sense for us to do that as well. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31nvme: flush dcache on both r/w, and the prp listPatrick Wildt
It's possible that the data cache for the buffer still holds data to be flushed to memory, since the buffer was probably used as stack before. Thus we need to make sure to flush it also on reads, since it's possible that the cache is automatically flused to memory after the NVMe DMA transfer happened, thus overwriting the NVMe transfer's data. Also add a missing dcache flush for the prp list. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31virtio: pci: use correct type in virtio_pci_bind()Heinrich Schuchardt
For printing as %u we should use an unsigned int. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31usb: ehci-hcd: Keep async schedule runningMarek Vasut
Profiling the EHCI driver shows a significant performance problem in ehci_submit_async(). Specifically, this function keeps enabling and disabling async schedule back and forth for every single transaction. However, enabling/disabling the async schedule does not take effect immediatelly, but instead may take up to 1 mS (8 uFrames) to complete. This impacts USB storage significantly, esp. since the recent reduction of maximum transfer size to support more USB storage devices. This in turn results in sharp increase in the number of ehci_submit_async() calls. Since one USB storage BBB transfer does three such calls and the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB, which is unacceptable. However, this overhead can be removed simply by keeping the async schedule running. Specifically, the first transfer starts the async schedule and then each and every subsequent transfer only adds a new QH into that schedule, waits until the QH is completed and does NOT disable the async schedule. The async schedule is stopped only by shutting down the controller, which must happen before moving out of U-Boot, otherwise the controller will corrupt memory. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
2019-10-31dfu: add callback for flush and initiated operationPatrick Delaunay
Add weak callback to allow board specific behavior - flush - initiated This patch prepare usage of DFU back end for communication with STM32CubeProgrammer on stm32mp1 platform with stm32prog command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: add DFU virtual backendPatrick Delaunay
Add a virtual DFU backend to allow board specific read and write (for OTP update for example). Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: add partition support for MTD backendPatrick Delaunay
Add the support of MTD partition for the MTD backend. The expected dfu_alt_info for one alternate on the mtd device : <name> part <part_id> <name> partubi <part_id> "partubi" also erase up to the end of the partition after write operation. For example: dfu_alt_info = "spl part 1;u-boot part 2; UBI partubi 3" U-Boot> dfu 0 mtd nand0 Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: add backend for MTD devicePatrick Delaunay
Add DFU backend for MTD device: allow to read and write on all MTD device (NAND, SPI-NOR, SPI-NAND,...) For example : > set dfu_alt_info "nand_raw raw 0x0 0x100000" > dfu 0 mtd nand0 This MTD backend provides the same level than dfu nand backend for NAND and dfu sf backend for SPI-NOR; So it can replace booth of them but it also add support of spi-nand. > set dfu_alt_info "nand_raw raw 0x0 0x100000" > dfu 0 mtd spi-nand0 The backend code is based on the "mtd" command introduced by commit 5db66b3aee6f ("cmd: mtd: add 'mtd' command") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: allow read with no data without error for EOF indicationPatrick Delaunay
This patch allows the DFU backend to indicate that that it can't provide no more data to fill the DFU buffer, by setting b_left =0 without error, even if the size of received data is lower of the expected total size indicated by get_medium_size. For USB DFU stack point of view, it is acceptable: the read length < requested size in DFU_UPLOAD and the transaction is stopped. That avoid infinite loop issue in dfu_read_buffer_fill because the size for the DFU read is limited by get_medium_size = r_left and the DFU stack expects that read is allowed up to this size. This issue never occurs for current flash device (where chunk are always completely read, and b_left will be never 0) but it is useful for virtual partition when the backend only know the max size of this alternate, the real size of the data are only known in the read treatment. PS: for file access on mmc, EOF is never reached as dfu_get_medium_size_mmc returns the exact size of the file. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: allow to manage DFU on several devicesPatrick Delaunay
Add support of DFU for several interface/device with one command. The format for "dfu_alt_info" in this case is : - <interface> <dev>'='alternate list (';' separated) - each interface is separated by '&' The previous behavior is always supported. One example for NOR (bootloaders) + NAND (rootfs in UBI): U-Boot> env set dfu_alt_info \ "sf 0:0:10000000:0=spl part 0 1;u-boot part 0 2; \ u-boot-env part 0 3&nand 0=UBI partubi 0,3" U-Boot> dfu 0 list DFU alt settings list: dev: SF alt: 0 name: spl layout: RAW_ADDR dev: SF alt: 1 name: ssbl layout: RAW_ADDR dev: SF alt: 2 name: u-boot-env layout: RAW_ADDR dev: NAND alt: 3 name: UBI layout: RAW_ADDR U-Boot> dfu 0 $> dfu-util -l Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\ intf=0, alt=3, name="UBI", serial="002700333338511934383330" Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\ intf=0, alt=2, name="u-boot-env", serial="002700333338511934383330" Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\ intf=0, alt=1, name="u-boot", serial="002700333338511934383330" Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\ intf=0, alt=0, name="spl", serial="002700333338511934383330" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: prepare the support of multiple interfacePatrick Delaunay
Split the function dfu_config_entities with 2 new functions - dfu_alt_init - dfu_alt_add Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: sf: add partition support for nor backendPatrick Delaunay
Copy the partition support from NAND backend to SF, support part and partubi option. In case of ubi partition, erase the rest of the partition as it is mandatory for UBI. The added code is under compilation flag CONFIG_DFU_SF_PART activated by default. for example: U-Boot> env set dfu_alt_info "spl part 0 1;\ u-boot part 0 2;u-boot-env part 0 3;UBI partubi 0 4" U-Boot> dfu 0 sf 0:0:10000000:0 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31dfu: cosmetic: cleanup sf to avoid checkpatch errorPatrick Delaunay
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31dwc3: flush cache only if there is a buffer attached to a requestMarek Szyprowski
Calling cache flush on invalid buffer, even with zero length might cause an exception on certain platforms. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2019-10-31dfu: mmc: add support for in-partition offsetMarek Szyprowski
Add possibility to define a part of partition as a separate DFU entity. This allows to have more than one items on the given partition. The real use case for this option is TM2 board. It can use u-boot stored as Linux kernel on the defined partition (as RAW data) and load the real kernel from the same partition, but stored under the certain offset. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31gadget: f_thor: properly enable 3rd endpoint defined by the protocolMarek Szyprowski
This is needed to make Windows THOR flash tool happy, because it starts sending data only when interrupt packet is received on the 3rd endpoint. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31dfu: dfu_nand: reduce verbosityRalph Siemsen
In combination with multiple partitions in NAND, this printf() ends up being more noise than helpful. Change it to debug() instead. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31dwc3-generic: Don't fail probe if clk/reset entries are absentVignesh Raghavendra
Some boards don't populate clk/reset entries as these are are optional as per binding documentation. Therefore, don't fail driver probe if clk/reset entries are absent in DT. This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx Fixes: e8e683d33b0c ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer") Reported-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-10-30gpio: da8xx_gpio: Fix the _gpio_direction_output functionKeerthy
_gpio_direction_output function currently calls gpio_set_value with the wrong gpio number. gpio_set_value in the uclass driver expects a different gpio number and the _gpio_direction_output is currently providing the number specific to the bank. Hence fix it by calling the _gpio_set_value function instead. Reported-by: Faiz Abbas <faiz_abbas@ti.com> Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci") Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-10-30Merge tag 'u-boot-clk-23Oct2019' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add I2C clocks for i.MX6Q CCF driver - Fix check in clk_set_default_parents() - Managed API to get clock from device tree - Fixes for core clock code (including sandbox regression tests)
2019-10-30blk: set log2blksz in blk_create_device()Heinrich Schuchardt
The ext4 file system requires log2blksz to be set. So when setting the block size on the block descriptor we should fill this field too. This fixes a problem with EFI block devices providing ext4 partitions, cf. https://lists.denx.de/pipermail/u-boot/2019-October/387702.html. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-30Merge tag 'mmc-10-29-2019' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc driver cleanup - spl_mmc bug fix to avoid access wrong emmc partition
2019-10-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
2019-10-29mmc: fsl_esdhc: drop i.MX DDR support codeYangbo Lu
A previous patch below adding DDR mode support was actually for i.MX platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC, it uses different process for DDR mode, and hasn't been supported. Let's drop DDR support code for i.MX in fsl_esdhc driver. 0e1bf61 mmc: fsl_esdhc: Add support for DDR mode Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29mmc: fsl_esdhc: remove redundant DM_MMC checkingYangbo Lu
Remove redundant DM_MMC checking which is already in DM_MMC conditional compile block. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29mmc: fsl_esdhc: make BLK as hard requirement of DM_MMCYangbo Lu
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already support it, so let's force to use it. - Drop non-BLK support for DM_MMC introduced by below patch. 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC). - Use DM_MMC instead of BLK for conditional compile. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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