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2019-11-22Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- Assorted fixes
2019-11-22Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- Fix some possible alignment issues
2019-11-22usb: dwc2: fix possible alignment issuesSimon Goldschmidt
Since upgrading to gcc9, warnings are issued: "taking address of packed member of ‘...’ may result in an unaligned pointer value" Fix this by converting dwc2_fifo_read to use unaligned access since packed structures may be on an unaligned address, depending on USB hardware. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-22usb: composite: fix possible alignment issuesSimon Goldschmidt
Since upgrading to gcc9, warnings are issued: "taking address of packed member of ‘...’ may result in an unaligned pointer value" Fix this by converting two functions to use unaligned access since packed structures may be on an unaligned address, depending on USB hardware. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20spi: cadence_qspi: support DM_CLKSimon Goldschmidt
Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20timer: dw-apb: add reset handlingSimon Goldschmidt
To use this DM timer on socfpga as system tick, it needs to take itself out of reset. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20ddr: socfpga: gen5: constify altera_gen5_sdram_opsSimon Goldschmidt
Make the function pointer struct const, as it does not need to be writable. This doesn't really change anything other than moving this variable to a different section. No functional change. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- Fix CONFIG_AHCI related build warning for P2041, P3041, P5040, T102x, T104x, T4240 platforms
2019-11-19input: Move input.o to be built only in some casesTom Rini
We only need to build and link input.o when we have any of CONFIG_KEYBOARD, CONFIG_DM_KEYBOARD (and SPL/TPL variants) or CONFIG_TEGRA_KEYBOARD set. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-19usb: cdns3: Fix include file pathVignesh Raghavendra
xhci.h has now been moved to include/usb/ directory. Therefore, update the path in the Cadence USB drivers. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-19ata: sata_sil: Add DM support for Silicon sata driverPeng Ma
Add DM support for Silicon(SIL3131 / SIL3132 / SIL3124) sata driver as few of the PowerPC platforms such as P series based boards need to use SATA_SIL with DM, Also fix below warning while PowerPC P series boards compilation, ===================== WARNING ======================" This board does use CONFIG_LIBATA but has CONFIG_AHCI not" enabled. Please update the storage controller driver to use" CONFIG_AHCI before the v2019.07 release." Failure to update by the deadline may result in board removal." See doc/driver-model/MIGRATION.txt for more info." ====================================================" Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19ata: fsl_sata: Add DM support for Freescale PowerPC SATA driverPeng Ma
Add DM support for Freescale PowerPC sata driver used for PowerPC T series SoCs, CONFIG_BLK needs to be enabled on these platforms. It adds the SATA controller as AHCI device, which is strictly speaking not correct, as the controller is not AHCI compatible, But the U-Boot AHCI uclass interface enables the usage of this DM driver, Also fix below warning while PowerPC T series boards compilation, ===================== WARNING ======================" This board does use CONFIG_LIBATA but has CONFIG_AHCI not" enabled. Please update the storage controller driver to use" CONFIG_AHCI before the v2019.07 release." Failure to update by the deadline may result in board removal." See doc/driver-model/MIGRATION.txt for more info." ====================================================" Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-18Merge tag 'video-for-v2020.01-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix i.MX6ULL evk black screen observed while reboot stress tests - remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree differences between Linux and U-Boot for stm32mp1 platform
2019-11-17Merge tag 'u-boot-rockchip-20191118' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip SoC: PX30, RK3308 - Add and migrate to use common dram driver: PX30, RK3328, RK3399 - Add rk3399 board Tinker-s support - Board config update for Rock960, Rockpro64
2019-11-17rockchip: rk3308: Add sdram driverAndy Yan
A dm based dram driver for rk3308 u-boot to get capacity. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: Add clk driver for rk3308Finley Xiao
Add clk controller driver for RK3308 SOC. This patch depends on Elaine's pll patch[0]. [0]http://patchwork.ozlabs.org/patch/1183718/ Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: pll: add common pll setting funcsElaine Zhang
Common PLL setup function, compatible with different SOC. Mainly for the subsequent new SOC use. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: fix wrong CONFIG_IS_ENABLED handlingHeiko Stuebner
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so without the leading CONFIG_. The clock drivers all wrongly check for CONFIG_RESET_ROCKCHIP, fix that Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: rv1108: remove duplicate reset initHeiko Stuebner
rockchip_reset_bind() already does the needed init for the reset registers, only referenced the wrong cru structure. So we can get rid of the open-coded reset init and just fix the correct cru reference. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: usb: Migrate to use ofnodeKever Yang
Migrate to use ofnode_* instead of fdt_* so that we may able to use live dt for usb udc driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17misc: add driver for the Rockchip otp controllerFinley Xiao
Newer Rockchip socs like the px30 use a different ip block to handle one-time-programmable memory, so add a misc driver for it as well. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17net: gmac_rockchip: add support for px30Heiko Stuebner
Add the glue code to allow the px30 variant of the Rockchip gmac to provide network functionality. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: add px30 clock driverKever Yang
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17pinctrl: rockchip: add px30 pinctrl driverDavid Wu
Add the necessary glue code to allow pinctrl setting on px30 socs. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Fix dram setting to make dram more stableYouMin Chen
There are some code different with rockchip vendor code which may lead to different bugs, including: 1) Fix setting error about LPDDR3 dram size ODT. 2) Set phy io speed to 0x2. 3) Fix setting error about phy_pad_fdbk_drive. 4) Fix setting error about PI_WDQLVL_VREF_EN Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update calculate_strideKever Yang
Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Sync the io setting from Rockchip vendor codeKever Yang
The io setting are updated after some bugfix in different rk3399 boards, sync the code from vendor. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: update lpddr4 timing for rk3399Kever Yang
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip vendor code; Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: add support detect capacityYouMin Chen
Add capacity detect for rk3399 so that the driver able to detect the capacity automatically. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update the function of sdram_initYouMin Chen
Clean up the sdram_init to keep sync with rockchip source code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: fix error about get_ddrc0_con reg addrYouMin Chen
Correct the register to its correct name. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Clean up codeYouMin Chen
Clean up rk3399 dram driver source code for more readable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: migrate to use common codeYouMin Chen
For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3328: use common sdram driverYouMin Chen
RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: px30: add sdram driverYouMin Chen
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add phy driver code for PX30Kever Yang
This sdram_phy_px30.c is based on PX30 SoC, the functions are common for phy, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add controller code for PX30Kever Yang
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common for controller, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: Default enable DRAM debug infoKever Yang
The debug info for dram is main about the capacity related info which is very important the board init, so set this default enable. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: move sdram_debug function into sdram_commonKever Yang
The functions for dram info print are part of common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add common code for sdram driverKever Yang
There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram_common.c/h to sdram.cKever Yang
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c; so that we can use the file name sdram_common.c in dram driver for better understand the code; clean the related file who has use the header file at the same time. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram.h to sdram_rk3288.hKever Yang
The header file sdram.h is used for rk3288 and similar SoCs, rename it to make it more understandable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-14pinctrol: dm: remove the function pinctrl_decode_pin_configPatrick Delaunay
Remove the pinctrl_decode_pin_config() API, because this function is unused and not compatible with livetree (it uses fdtdec_get_bool instead of ofnode API). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-12video: stm32: remove the compatible "synopsys, dw-mipi-dsi" supportPatrick Delaunay
Remove the compatible "synopsys,dw-mipi-dsi" added in U-Boot (it don't exist in Linux kernel binding); it is only used to bind the generic synopsys UCLASS_DSI_HOST "dw_mipi_dsi" to the driver "stm32-display-dsi" UCLASS_VIDEO_BRIDGE This binding is done in Linux kernel drivers without compatible (dw_mipi_dsi_bind() is called in bind of driver, for example in drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c). This patch does the same in U-Boot driver, the STM32 driver calls during its bind the function device_bind_driver_to_node to bind the generic driver "dw_mipi_dsi" at the same address. This patch reduces the device tree differences between Linux kernel and U-Boot for stm32mp1 platform. Tested with v2020.01-rc1 on STM32MP157C-EV1 and STM32MP157C-DK2. The dependency of driver is clearer and the probe order is guaranteed. STM32MP> dm tree Class Index Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver sysreset 0 [ ] syscon_reboot |-- reboot simple_bus 0 [ + ] generic_simple_bus |-- soc serial 0 [ + ] serial_stm32 | |-- serial@40010000 ... video_brid 0 [ + ] stm32-display-dsi | |-- dsi@5a000000 dsi_host 0 [ + ] dw_mipi_dsi | | |-- dsihost panel 0 [ + ] rm68200_panel | | `-- panel-dsi@0 ... Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-11-12Merge tag 'u-boot-imx-20191105' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191105 ------------------- i.MX8MN SoC support ROM API image download support i.MX8MM enet enabling
2019-11-12video: mxsfb: Configure the clock after eLCDIF resetFabio Estevam
Running stress reboot test on a i.MX6ULL evk board with a custom LCD can lead to splash screen failure (black screen). After comparing the eLCDIF initialization with the Linux kernel driver, it was noticed that the eLCDIF reset is the first operation that needs to be done. So do like the eLCDIF Linux driver and move the eLCDIF clock frequency configuration after the eLCDIF reset and just prior to setting the RUN bit. With this change applied, no more black screen issues has been found during overnight reboot stress tests. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-11-11Merge tag 'u-boot-rockchip-20191110' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000 - Fix the u8 type comparision with '-1'. - Fix checkpatch warning for multi blank line and review signature.
2019-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC. - Few bug fixes and updates related to SPI, hwconfig, ethernet, fsl-layerscape, pci, icid, PSCI
2019-11-10ram: rk3328: Fix loading of skew valuesSimon South
Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10ram: rk3328: Use correct frequency units in functionSimon South
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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