summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2019-04-12ag7xxx: add initial support for s17Rosy Song
S17 ethernet support is for QCA8337N, which used on AP152 (QCA9563) board. It is a 7 ports GbE switch. Signed-off-by: Rosy Song <rosysong@rosinson.com> Changes for v2-v3: - add more commit message for s17 Changes for v4-v5: - coding style cleanup
2019-04-12dma: bcm6348: check if driver is enabled before send/recvÁlvaro Fernández Rojas
This patch prevents errors when running tftpput. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-04-12net: mscc: ocelot: Fix reset of the physHoratiu Vultur
The function mscc_miim_reset resets all the phys, but it is called for each phy separetely. One consequence of this is that the boot time is increased by 2 seconds. The fix consists for calling the mscc_miim_reset function only once for all phys. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12drivers: add ethernet support for qca953x in ag7xxx driverRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12drivers: fix typo for pinctrl qca953xRosy Song
Signed-off-by: Rosy Song <rosysong@rosinson.com>
2019-04-12mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driverChristophe Kerello
The driver adds the support for the STMicroelectronics FMC2 NAND Controller found on STM32MP SOCs. This patch adds the polling mode, a basic mode that do not need any DMA channels. Only NAND_ECC_HW mode is actually supported. The driver supports a maximum 8k page size. The following ECC strength and step size are currently supported: - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC based on Hamming) This patch has been tested on Micron MT29F8G08ABACAH4. Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2019-04-12spi: stm32_qspi: move to exec_opChristophe Kerello
We are facing issues in the driver since SPI NOR framework has moved on SPI MEM framework, and SPI NAND framework is not running properly with the current driver. To be able to solve issues met on SPI NOR Flashes and to be able to support SPI NAND Flashes, the driver has been reworked. We are now using exec_op ops instead of using xfer ops. Thanks to this rework, the driver has been successfully tested with: - mx66l51235l SPI NOR Flash on stm32f746 SOC - n25q128a SPI NOR Flash on stm32f769 SOC - mx66l51235l SPI NOR Flash on stm32mp1 SOC - mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-12pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driverPatrick Delaunay
This patch adds pinctrl/GPIO driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander. STMFX is an I2C slave controller, offering up to 24 GPIOs. The driver relies on UCLASS_PINCTRL and UCLASS_GPIO. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12stpmic1: add NVM update support in fuse commandPatrick Delaunay
Add functions to read/update the non volatile memory of STPMIC1 (8 bytes-register at 0xF8 address) and allow access with fuse command (bank=1, word > 0xF8). For example: STM32MP> fuse read 1 0xf8 8 Reading bank 1: Word 0x000000f8: 000000ee 00000092 000000c0 00000002 Word 0x000000fc: 000000f2 00000080 00000002 00000033 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12pmic: stpmu1: add power switch off supportPatrick Delaunay
Add sysreset support, and support power switch off request, needed by poweroff command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stpmic1: update register namesPatrick Delaunay
Alignment with STPMIC1 datasheet s/MAIN_CONTROL_REG/MAIN_CR/g s/MASK_RESET_BUCK/BUCKS_MRST_CR/g s/MASK_RESET_LDOS/LDOS_MRST_CR/g s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g s/VREF_CTRL_REG/REFDDR_MAIN_CR/g s/LDOX_CTRL_REG/LDOX_MAIN_CR/g s/USB_CTRL_REG/BST_SW_CR/g s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g and update all the associated defines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12power: rename stpmu1 to official name stpmic1Patrick Delaunay
Alignment with kernel driver name & binding introduced by https://patchwork.kernel.org/cover/10761943/ to use the final marketing name = STPMIC1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12power: stpmu1: rename files to stpmic1Patrick Delaunay
Prepare file modification for kernel alignment and rename driver to stpmic1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-04-12regulator: stpmu1: update buck1 rangePatrick Delaunay
SW impact for Rev 1.2 of STPMIC1 in U-Boot: Buck converters output voltage change for Buck1 => Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V (see STPMIC1 datasheet / chapter 5.3 Buck converters) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12stm32mp1: add trusted boot with TF-APatrick Delaunay
Add support of trusted boot, using TF-A as first stage bootloader, The boot sequence is BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32 The TF-A monitor provides secure monitor with support of SMC - proprietary to manage secure devices (BSEC for example) - PSCI for power The same device tree is used for STMicroelectronics boards with basic boot and with trusted boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-12mtd: spi-nor-ids: Add Gigadevice gd25lq128 IDNeil Armstrong
This adds support for the Gigadevice gd25lq128 ID needed on the upcoming libretech-ac board. SPI_NOR_QUAD_READ is not set since it has not been tested in Quad mode. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mmc: omap_hsmmc: Set 3.3V for IO voltageFaiz Abbas
Pbias voltage should match the IO voltage set for the SD card. With the latest pbias change to 3.3V, update the capabilities and IO voltages settings to 3.3V. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12ARM: dts: dra7: Change pbias voltage to 3.3VFaiz Abbas
As per recent TRM[1], PBIAS cell on dra7 devices supports 3.3v and not 3.0v as documented earlier. Update PBIAS regulator max voltage and the voltage written in the driver to reflect this. [1] http://www.ti.com/lit/pdf/sprui30 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12board: ti: am335x: Add platdata for cpsw in SPLFaiz Abbas
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL is enabled. Use static platdata instead to save space. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Enable DM_FLAG_PRE_RELOCFaiz Abbas
Add DM_FLAG_PRE_RELOC to make the driver probe in SPL. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Block off ofdata_to_platdata with OF_CONTROLFaiz Abbas
The ofdata_to_platdata function should not be called if OF_CONTROL is not enabled because fdtdec_* calls will fail. Block the function with OF_CONTROL Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw-common: Isolate getting syscon address from assigning macidFaiz Abbas
ti_cm_get_macid() is used to get a syscon node from the dt, read the efuse address and then assign the macid read from the address. Divide these two steps into separate functions one of which can be called from ofdata_to_platdata() while the other can be called from _probe(). This ensures that platdata can be assigned statically in a board file when OF_CONTROL is not enabled. Also add a macid_sel_compat in private data to get information about the macid byte placement. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Convert cpsw_platform_data to a pointer in cpsw_privFaiz Abbas
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it dynamically and assign it as a part of eth_pdata. This helps in isolating platform data handling and implementing platdata for SPL in a board file. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12net: ti: cpsw: Move cpsw_phy_sel() to _probe()Faiz Abbas
cpsw_phy_sel() is a configuration step that should not be in ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data structure so that it is accessible in _probe. Then move the call of cpsw_phy_sel() to _probe. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-04-12firmware: Add support for querying msmc memoryLokesh Vutla
DMSC can use certain amount of msmc memory available in the system. Also certain part of msmc memory can be marked as L3 cache using board config. But users might not know what size is being used and the remaining available msmc memory. In order to fix this TISCI protocol provides a messages that can query the available msmc memory in the system. Add support for this message. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12net: netcp: add support for phy with rgmii idsMurali Karicheri
Enhance the netcp driver to support phys that can be configured for internal delay (rgmii-id, rgmii-rxid, rgmii-txid) Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-12dm: spi: Read default speed and mode values from DTPatrick Delaunay
This patch update the behavior introduced by commit 96907c0fe50a ("dm: spi: Read default speed and mode values from DT") In case of DT boot, don't read default speed and mode for SPI from CONFIG_* but instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Remove also use in boards of the value speed=0 (no more supported) for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0. DT values will be always used when available (full DM support of SPI slave with available DT node) even if speed and mode are requested; for example in splash screen support (in splash_sf_read_raw) or in SPL boot (in spl_spi_load_image). The caller of spi_get_bus_and_cs() no more need to force speed=0. But the current behavior don't change if the SPI slave is not present (device with generic driver is created automatically) or if platdata is used (CONFIG_OF_PLATDATA). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: spi: Replace ad-hoc default implementation with spi_mem_opMarek Vasut
Replace the ad-hoc erase operation implementation with a simple spi_mem_op implementation of the same functionality. This is a minor optimization and removal of the ad-hoc code. This however also changes the behavior of the execution of the erase opcode from two separate transfer requests to the SPI NOR driver to one transfer request to the SPI NOR driver. The former was how U-Boot behaved before the SPI NOR framework was imported and the later was introduced by the SPI NOR framework. The former is more optimal, so keep that. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Horatiu Vultur <horatiu.vultur@microchip.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com> Tested-by: Ashish Kumar <Ashish.kumar@nxp.com>
2019-04-12spi: fsl_dspi fix to stop extra transmissionsJared Bents
Update to prevent a byte of zeros being transmitted between each byte in the tx buffer when providing both a tx buffer and a rx buffer. Signed-off-by: Jared Bents <jared.bents@rockwellcollins.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12spi: spi-mem: Check if exec_op function is set before calling itBernhard Messerklinger
Add check if exec_op is set before calling it. At the moment it is called unconditionally, which leads to a crash if it is not set correctly. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: fix Coverity integer handling issueMiquel Raynal
A Coverity robot reported an integer handling issue (OVERFLOW_BEFORE_WIDEN) in the potentially overflowing expression: (mtd_div_by_ws(mtd->size, mtd) - mtd_div_by_ws(offs, mtd)) * mtd_oobavail(mtd, ops) While such overflow will certainly never happen due to the numbers handled, it is cleaner to fix this operation anyway. The problem is that all the maths include 32-bit quantities, while the result is stored in an explicit 64-bit value. As maxooblen will just be compared with a size_t, let's change the type of the variable to a size_t. This will not fix anything but will clarify a bit the situation. Then, do an explicit cast to fix Coverity warning. Addresses-Coverity-ID: 184180 ("Integer handling issues") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-12mtd: spi: Add Macronix MX66U2G45F deviceMarek Vasut
Add Macronix MX66U2G45F flash device description. This is a 256 MiB part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Vignesh R <vigneshr@ti.com> [jagan: use 'g' instead of 'f' in flash name] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: sf_probe: remove spi-flash compatibleNeil Armstrong
Now the "spi-flash" compatible has been removed in the DTS files, remove this compatible from sf_probe to finally use the Linux "jedec,spi-nor" compatible. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12mtd: add spi flash id s25fl064lHeiko Schocher
Add support for SPANSION s25fl064l Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Vignesh R <vigneshr@ti.com>
2019-04-12mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux versionStefan Roese
This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support with the latest Linux version (v5.0-rc3) plus the chip supported posted on the MTD list. Only the currently in U-Boot available chip is supported with this sync. The changes for the GD5F1GQ4UExxG are: - Name of NAND device changed to better reflect the real part - OOB layout changed to only reserve 1 byte for BBT - Use ECC caps 8bits/512bytes instead of 8bits/2048bytes - Enhanced ecc_get_status() function to determine and report a more fine grained bit error status Signed-off-by: Stefan Roese <sr@denx.de> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-12spi: cadence_qspi: Add quad write supportLey Foon Tan
Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12arm: mvebu: Add Marvell's integrated CPUsChris Packham
Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12sata: sata_mv: add orion-sata compatible stringMichael Walle
The kirkwood devices are compatible with this driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12sata: sata_mv: support kirkwood architectureMichael Walle
Fix the worng include and offset macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12sata: sata_mv: use correct format specifier in debug()Michael Walle
This fixes a compile error on kirkwood. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12ata: ahci_mvebu: add support for Armada 38xBaruch Siach
With board_ahci_enable() implementation for Armada 38x in place we can now enable 38x support in the ahci_mvebu driver. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12sata: sata_mv: Add DM support to enable CONFIG_BLK usageStefan Roese
This patch adds DM support to the Armada XP SATA driver. This is needed to enable CONFIG_BLK on this platform. It adds the SATA controller as AHCI device, which is strictly speaking not correct, as the controller is not AHCI compatible. But the U-Boot AHCI uclass interface enables the usage of this DM driver and the creation of the corresponding BLK devices. This conversion is done to get rid of the compile warning: Reviewed-by: Chris Packham <judge.packham@gmail.com> ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2019-04-12watchdog: orion_wdt: take timeout value in msChris Packham
The generic wdt_start API expects to be called with the timeout in milliseconds. Update the orion_wdt driver to accept a timeout in milliseconds and use the clock rate specified in the dts to convert the timeout to an appropriate value for the timer reload register. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-12watchdog: orion_wdt: support SPL usageChris Packham
When run from the SPL the mvebu targets are using the hardware default offset for the SoC peripherals. devfdt_get_addr_size_index() understands how to deal with this via dm_get_translation_offset() so use this instead of fdtdec_get_addr_size_auto_noparent(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-11dm: remove unused function dm_fdt_pre_relocPatrick Delaunay
The function dm_ofnode_pre_reloc should be used instead of the function dm_fdt_pre_reloc and avoid duplicated code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay
Prepare to remove dm_fdt_pre_reloc function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11clk: at91: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay
Prepare to remove dm_fdt_pre_reloc Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-11core: ofnode: Fix ASAN-reported stack-buffer-overflow in of_get_addressEugeniu Rosca
v2019.04-rc3 sandbox U-Boot fails to boot when compiled with -fsanitize=address and linked against -lasan, reporting [1]. Git bisecting shows that the issue is contributed by v2019.01 commit 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function"). The root cause seems to be the mismatch between sizeof(u64) and sizeof(fdt_size_t) on sandbox. Luckily, thanks to the fact that the size argument of both of_get_address() and fdtdec_get_addr_size_fixed() is optional, we can pass NULL in its place, avoiding the problem. [1] Backtrace reported by ASAN (gcc 8.1.0): $> ./u-boot -d arch/sandbox/dts/sandbox.dtb [..] Reviewed-by: Simon Glass <sjg@chromium.org> ================================================================= ==10998==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7ffcc2331140 at pc 0x0000004eeeb0 bp 0x7ffcc2330f80 sp 0x7ffcc2330f70 WRITE of size 8 at 0x7ffcc2331140 thread T0 #0 0x4eeeaf in of_get_address drivers/core/of_addr.c:154 #1 0x4f7441 in ofnode_get_addr_index drivers/core/ofnode.c:263 #2 0x5b2a78 in sb_eth_ofdata_to_platdata drivers/net/sandbox.c:422 #3 0x4dccd8 in device_probe drivers/core/device.c:407 #4 0x753170 in eth_initialize net/eth-uclass.c:428 #5 0x47d9bf in initr_net common/board_r.c:557 #6 0x6bcfa7 in initcall_run_list lib/initcall.c:30 #7 0x47e1fe in board_init_r common/board_r.c:859 #8 0x4060e5 in main arch/sandbox/cpu/start.c:356 #9 0x7fb8d135482f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f) #10 0x40a3a8 in _start (/path/to/u-boot/u-boot+0x40a3a8) Address 0x7ffcc2331140 is located in stack of thread T0 at offset 32 in frame #0 0x4f72b8 in ofnode_get_addr_index drivers/core/ofnode.c:255 This frame has 3 object(s): [32, 36) 'size' <== Memory access at offset 32 partially overflows this variable [96, 100) 'flags' [160, 168) 'node' HINT: this may be a false positive if your program uses some custom stack unwind mechanism or swapcontext (longjmp and C++ exceptions *are* supported) SUMMARY: AddressSanitizer: stack-buffer-overflow drivers/core/of_addr.c:154 in of_get_address Shadow bytes around the buggy address: 0x10001845e1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e1f0: 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 0x10001845e200: 04 f2 f2 f2 f2 f2 f2 f2 04 f2 f2 f2 f2 f2 f2 f2 0x10001845e210: 04 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 00 00 =>0x10001845e220: 00 00 00 00 f1 f1 f1 f1[04]f2 f2 f2 f2 f2 f2 f2 0x10001845e230: 04 f2 f2 f2 f2 f2 f2 f2 00 f2 f2 f2 f3 f3 f3 f3 0x10001845e240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x10001845e250: 00 00 00 00 f1 f1 f1 f1 00 00 f2 f2 f3 f3 f3 f3 0x10001845e260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 0x10001845e270: f1 f1 00 f2 f2 f2 f3 f3 f3 f3 00 00 00 00 00 00 Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb ==10998==ABORTING 'To' list: git log --since=1year drivers/core/ofnode.c | grep "\-by: .*@" | \ sed 's/.*-by: //' | sort | uniq -c | sort -rn 10 Simon Glass <sjg@chromium.org> 3 Mario Six <mario.six@gdsys.cc> 2 Martin Fuzzey <mfuzzey@parkeon.com> 2 Marek Vasut <marek.vasut+renesas@gmail.com> 1 Tom Rini <trini@konsulko.com> 1 Masahiro Yamada <yamada.masahiro@socionext.com> 1 Keerthy <j-keerthy@ti.com> 1 Jens Wiklander <jens.wiklander@linaro.org> 1 Bin Meng <bmeng.cn@gmail.com> Fixes: 1678754f5e2c ("core: ofnode: Fix ofnode_get_addr_index function") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-04-11sysreset: use syscon_regmap_lookup_by_phandlePatrick Delaunay
Use the new function syscon_regmap_lookup_by_phandle() to simplify the code. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-11syscon: update syscon_regmap_lookup_by_phandlePatrick Delaunay
Change the function syscon_regmap_lookup_by_phandle() introduced by commit 6c3af1f24e4b ("syscon: dm: Add a new method to get a regmap from DTS") to have Linux-compatible syscon API. Same modification than commit e151a1c288bd ("syscon: add Linux-compatible syscon API") solves issue when the node identified by the phandle has several compatibles and is already bound to a dedicated driver. See Linux commit bdb0066df96e ("mfd: syscon: Decouple syscon interface from platform devices"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-06 21:25:33 +0000