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2019-07-25net: macb: add support for faster clk ratesRamon Fried
add support for clock rates higher than 2.4Mhz Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25net: macb: sync header definitions as taken from LinuxRamon Fried
Few registers and bits were added by Cadence and they were not updated in the headers. Take the latest definitions as defined in Linux header (5.1) that also includes some comments about existing registers. One register was improperly named (UR), fix that. Signed-off-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: driver for MDIO muxes controlled over I2CAlex Marginean
This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-25net: designware: use 'phy_connect' instead of open codedSimon Goldschmidt
Using 'phy_connect' instead of 'phy_find_by_mask' and 'phy_connect_dev' both deduplicates code and adds support for 'fixed-link'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: fsl_enetc: add support for SGMII 2500Alex Marginean
SGMII 2500 as supported on NXP SoCs requires AN to be disabled, handle this case in the enetc sgmii init code. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: apply serdes configuration for ENETC Ethernet interfacesAlex Marginean
Ethernet interfaces using serial protocols go through the serdes block integrated in the SoC. This is accessed over dedicated internal MDIOs which are part of the Ethernet PCI functions. Set up serdes at _start, along with other protocol specific port/MAC configuration. MDIO code is shared with enetc_mdio, read/write functions are exported from fsl_enetc_mdio for this reason. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: add NXP ENETC MDIO driverAlex Marginean
Adds a driver for the MDIO interface currently integrated in LS1028A SoC. This MDIO interface is shared by multiple ethernet interfaces and is presented as a stand-alone PCI function on the SoC ECAM. Ethernet has a functional dependency on MDIO, for simplicity there is a single config option for both. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25drivers: net: add NXP ENETC ethernet driverAlex Marginean
Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-25spi: Drop obsolete mtk_qspi driver referencesWeijie Gao
Since u-boot has added the spi-mem framework and replaced the spi-nor framework, the mtk_qspi is no longer compatible with the new spi-nor driver. Remove this driver along with replacing config item with new mtk spi-nor driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> [jagan: squash related changes and update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-25spi: add spi-mem driver for MediaTek MT7629 SoCWeijie Gao
This patch adds spi-mem driver for MediaTek MT7629 SoC to access SPI-NOR and SPI-NAND flashes. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> [jagan: squash MAINTAINERS file] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-24dm: device: make power domain calls optionalAnatolij Gustschin
Reduce power domain calls when CONFIG_POWER_DOMAIN is disabled. With gcc v8.2, this change saves 104 bytes. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-24clk: initialize clk->data when using default xlateSekhar Nori
Right now when using clk_of_xlate_default(), clk->data remains un-initialized because clk_get_bulk() does not initialize memory on allocation of clock structure. This can cause problems when data is used to match if two clocks pointers are exactly the same underlying clocks, for example. Fix it by initializing clk->data to 0. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-24dm: core: Set correct "status" value for a nodeBin Meng
Per device tree spec, "status" property can have a value of "okay", or "disabled", but not "disable". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-24dm: core: Call clk_set_defaults() during probe() only for a valid ofnodeBin Meng
Without a valid ofnode, it's meaningless to call clk_set_defaults() to process various properties. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-24dm: timer: Skip device that does not have a valid ofnode in pre_probe()Bin Meng
It is possible that a timer device has a null ofnode, hence there is no need to further parse DT for the clock rate. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-07-23Merge tag 'u-boot-stm32-20190723' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - add rtc driver for stm32mp1 - add remoteproc driver for stm32mp1 - use kernel qspi compatible string for stm32
2019-07-23Merge tag 'rockchip-for-v2019.07-2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 sdhci driver fixup - TPL BANNER fixup
2019-07-22mtd: spi: Add micron mt35xu512aba and mt35xu02g flash IDAshish Kumar
mt35xu512aba and mt35xu02g suports Single I/O and OCTAL I/O also enable use of SPI_NOR_4B_OPCODES. These flashes are tested on LX2160ARDB and LS1028ARDB respectively Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [jagan: suffix 'ba' on part name and update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-22rtc: Add rtc driver for stm32mp1Patrick Delaunay
Add support of STM32MP1 rtc driver. Enable it for basic and trusted configurations. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
2019-07-22clk: stm32mp1: Add RTC clock entryPatrick Delaunay
Add RTCAPB and RTC clock support. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-22spi: stm32_qspi: Remove "st, stm32-qspi" compatible stringPatrice Chotard
"st,stm32-qspi" is no more used, remove it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-07-22remoteproc: Introduce STM32 Cortex-M4 remoteproc driverFabien Dessenne
This patch introduces support of Cortex-M4 remote processor for STM32 MCU and MPU families. Signed-off-by: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-07-22remoteproc: add elf file load supportFabien Dessenne
The current implementation supports only binary file load. Add helpers to support ELF32 format (sanity check, and load). Note that since an ELF32 image is built for the remote processor, the load function uses the device_to_virt ops to translate the addresses. Implement a basic translation for sandbox_testproc. Add related tests. Test result: => ut dm remoteproc_elf Test: dm_test_remoteproc_elf: remoteproc.c Test: dm_test_remoteproc_elf: remoteproc.c (flat tree) Failures: 0 Signed-off-by: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-22dm: core: Introduce xxx_translate_dma_address()Fabien Dessenne
Add the following functions to translate DMA address to CPU address: - dev_translate_dma_address() - ofnode_translate_dma_address() - of_translate_dma_address() - fdt_translate_dma_address() These functions work the same way as xxx_translate_address(), with the difference that the translation relies on the "dma-ranges" property instead of the "ranges" property. Add related test. Test report: => ut dm fdt_translation Test: dm_test_fdt_translation: test-fdt.c Test: dm_test_fdt_translation: test-fdt.c (flat tree) Failures: 0 Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-07-21Merge tag 'rockchip-for-v2019.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3399 lpddr4 support - rk3399-rock960 board support improvement - Eliminate pyelftools dependency by make_fit_atf.py - clean up rockchip dts to use -u-boot.dtsi - use ARM arch/generic timer instead of rk_timer - clean up Kconfig options for board support
2019-07-21fpga: arria10: Fix error in fpga pin configurationDalon Westergreen
Pin configuration of the FPGA devicetree block should be done after core configuration in the arria10 fpga driver. This fix corrects the check of status, and ensures that the fpga pin mux is configured on correct configuration of the core fpga image. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
2019-07-21spl: kconfig: separate sysreset and firmware drivers from miscSimon Goldschmidt
This adds separate kconfig options for drivers/sysreset and drivers/firmware. Up to now, CONFIG_SPL_DRIVERS_MISC_SUPPORT added drivers/misc to SPL build but also added drivers/firmware and drivers/sysreset at the same time. Since that is confusing, this patch uses CONFIG_SPL_SYSRESET for drivers/sysreset and adds CONFIG_SPL_FIRMWARE for drivers/firmware (and accordingly for the TPL options). CONFIG_SPL_DRIVERS_MISC_SUPPORT stays for including drivers/misc into the SPL build (and accordingly for TPL) since there are boards using non-DM (non UCLASS_MISC) files from drivers/misc. Such boards don't have CONFIG_SPL_MISC enabled, so cannot use this to include drivers/misc into the SPL build. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-07-21sysreset: add support for socfpga sysresetSimon Goldschmidt
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga to a UCLASS_SYSRESET based dm driver. A side effect is that gen5 and a10 can now select between cold and warm reset. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-07-21sysreset: socfpga: stratix10: add sysreset driverSimon Goldschmidt
This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-07-21sysreset: socfpga: gen5: add sysreset driverSimon Goldschmidt
This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-07-21dm: ddr: socfpga: fix gen5 ddr driver to not use bssSimon Goldschmidt
This driver uses bss from SPL board_init_f(). Change it to move all the data from bss to a common struct allocated on the stack (64 byte). In addition to saving 28 bytes of bss, the code even gets 264 bytes smaller. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-07-20rockchip: sdhci: Fix sdhci mmc driver probe abortKever Yang
This patch fix mmc driver abort caused by below patch: 3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask After the patch sdhci_setup_cfg() access to host->mmc->dev, so we have to do init before make the call to the function() Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20rockchip: video: rk3288_hdmi: Add missing call to dw_hdmi_enable()Niklas Schulze
The RK3288 HDMI driver's rk3288_hdmi_enable() currently lacks a call to dw_hdmi_enable(). Thus, the HDMI output never gets enabled. Signed-off-by: Niklas Schulze <me@jns.io> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-07-20rockchip: rk322x: sdram: use udelay instead of rockchip_udelayKever Yang
Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Add lpddr4 set rate supportJagan Teki
Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add set_rate sdram rk3399 opsJagan Teki
DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDDR4-800 timings incJagan Teki
LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDDR4-400 timings incJagan Teki
LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Add LPPDR4 mr detectionJagan Teki
Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held. Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization. So, add code to support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Handle data training via opsJagan Teki
data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-21ram: rk3399: Simplify data training first argumentJagan Teki
data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition. This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 vref_mode_acJagan Teki
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8% Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 mode_sel based on io settingsJagan Teki
The mode_sel on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Update lpddr4 vref based on io settingsJagan Teki
The vref_mode_dq, vref_value_dq on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Get lpddr4 tsel_rd_en from io settingsJagan Teki
For base.odt 1 the lpddr4 tsel_rd_en value is depending on IO settings of rd_odt_en. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: rk3399: Configure soc odt supportJagan Teki
CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399. These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2019-07-20ram: rk3399: Add tsel control clock driveJagan Teki
tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20ram: sdram: Configure lpddr4 tsel rd, wr based on IO settingsJagan Teki
Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
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