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2019-04-12firmware: Add support for querying msmc memoryLokesh Vutla
DMSC can use certain amount of msmc memory available in the system. Also certain part of msmc memory can be marked as L3 cache using board config. But users might not know what size is being used and the remaining available msmc memory. In order to fix this TISCI protocol provides a messages that can query the available msmc memory in the system. Add support for this message. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-12net: netcp: add support for phy with rgmii idsMurali Karicheri
Enhance the netcp driver to support phys that can be configured for internal delay (rgmii-id, rgmii-rxid, rgmii-txid) Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-11soc: keystone: Merge into ti specific directoryVignesh R
Merge drivers/soc/keystone/ into drivers/soc/ti/ and convert CONFIG_TI_KEYSTONE_SERDES into Kconfig. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-11dma: ti: add driver to K3 UDMAVignesh R
The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet mode) - MEM_TO_DEV (Packet mode) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11soc: ti: k3: add navss ringacc driverGrygorii Strashko
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11firmware: ti_sci: Add support for NAVSS resource managementGrygorii Strashko
Texas Instruments' System Control Interface (TI-SCI) Message Protocol abstracts management of NAVSS resources, like PSI-L pairing and unpairing, UDMAP tx/rx/flow configuration and Rings. This patch adds support for requesting and configuring such resources from TI-SCI firmware. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
2019-04-11Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various rmobile fixes
2019-04-09net: sh_eth: Initialize PHY in probe() onceMarek Vasut
Reset and initialize the PHY once in the probe() function rather than doing it over and over again is start() function. This requires us to keep the clock enabled while the driver is in use. This significantly reduces the time between transfers as the PHY doesn't have to restart autonegotiation between transfers, which takes forever. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
2019-04-09pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen3 pin control tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen2 pin control tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Add TDSEL fixup for H2/E2 ES1.0 SoCsMarek Vasut
Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783, has a TDSEL fix for R8A7790 H2 and R8A7794 E2 SoCs, implement similar fix for U-Boot. The difference here is that the SoC ES matching has to be implemented manually. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Synchronize Gen2 tables with Linux 5.0Marek Vasut
Synchronize R-Car Gen2 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Add R8A77965 pin control tablesMarek Vasut
Add pin control tables for R8A77965 from Linux 5.0 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut
Add clock tables for R8A77965 from Linux 5.0 , except for the crit, R and Z clock, which are neither used nor supported by the U-Boot clock framework yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini
2019-04-09usb: ehci-mx6: Use common code to extract dr_modeAdam Ford
There exists code in drivers/common/common.c to read the dr_mode from the device tree. This patch converts this driver to use that function to initialize the driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-09usb: host: Print device name when scanningIsmael Luceno Cortes
Drop the counter, it has no meaning other than being the order in which the interface is found; the name assigned to the USB host controller interface is a better indicator. Example of the original output: > USB0: USB EHCI 1.10 > scanning bus 0 for devices... 2 USB Device(s) found > scanning usb for storage devices... 1 Storage Device(s) found Patched output: > Bus usb@ee080100: USB EHCI 1.10 > scanning bus usb@ee080100 for devices... 2 USB Device(s) found > scanning usb for storage devices... 1 Storage Device(s) found Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
2019-04-09net: macb: Add small delay after link establishmentStefan Roese
I've noticed that the first ethernet packet after PHY link establishment is not tranferred correctly most of the time on my AT91SAM9G25 board. Here I usually see a timeout of a few seconds, which is quite annoying. Adding a small delay (10ms in this case) after the link establishment helps to solve this problem. With this patch applied, this timeout on the first packet is not seen any more. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wenyou Yang <wenyou.yang@atmel.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-09pinctrl: at91: add slewrate support for SAM9X60Claudiu Beznea
Add slew rate support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09pinctrl: at91: add compatibles for SAM9X60 pin controllerClaudiu Beznea
Add compatibles for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09pinctrl: at91: add drive strength support for SAM9X60Claudiu Beznea
Add drive strength support for SAM9X60 pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09pinctrl: at91: add option to use drive strength bitsClaudiu Beznea
SAM9X60 uses high and low drive strengths. To implement this, in at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of drive strengths (1 for low, 2 for high), thus change the code to allow the usage of drive strength bit numbers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2019-04-09arm: at91: Enable watchdog supportStefan Roese
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUTStefan Roese
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any more. The WD timeout value can be provided via the "timeout-sec" DT property. If not provided this way, the default value of 2 seconds will be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()Stefan Roese
This patch fixes the timer register setup in at91_wdt_start() to correctly configure the register again. The input timeout value is now in milli-seconds instead of seconds with the new watchdog API. Make sure to take this into account and only use a max timeout value of 16 seconds as appropriate for this SoC. Also the check against a lower timeout value than 0 is removed. This check makes no sense, as the timeout value is unsigned. Signed-off-by: Stefan Roese <sr@denx.de> Reported-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
2019-04-09serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIALStefan Roese
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image. Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected. This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-09mtd: ubi, ubifs debug: Use pr_debug instead of pr_critEran Matityahu
Before printk.h was introduced and MTDDEBUG was removed, pr_crit() was calling MTDDEBUG(), which was since then replaced by the current pr_debug(). pr_debug is more appropriate here. Signed-off-by: Eran Matityahu <eran.m@variscite.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-09mtd: ubi debug: Remove the pid print from ubi_assertEran Matityahu
Add a new definition for ubi_assert and keep the original one in an ifndef __UBOOT__. Signed-off-by: Eran Matityahu <eran.m@variscite.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-08net: dm: fec: Support phy-reset-post-delay propertyAndrejs Cainikovs
As per Linux kernel DT binding doc: - phy-reset-post-delay : Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay milliseconds will be observed after the phy-reset-gpios has been toggled. Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-04-07net: phy: implement fallback mechanism for negative phy adressesHannes Schmelzer
Negative phy-addresses can occour if the caller function was not able to determine a valid phy address (from device-tree for example). In this case we catch this here and search for ANY phy device on the given mdio- bus. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Lukasz Majewski <lukma@denx.de>
2019-04-03phy: Also allow MESON_GXM for MESON_GXL_USB_PHYNeil Armstrong
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs. Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-01clk: sunxi: a10: Add CLK_AHB_GMACJagan Teki
CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-31Merge tag 'video-fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-videoTom Rini
sunxi HDMI clock fix
2019-03-31Merge tag 'rockchip-fixes-for-2019.04' of git://git.denx.de/u-boot-rockchipTom Rini
Last-minute fixes for Rockchip for 2019.04: - reverts the deprecation of the 'download-key' detection (with a full solution pending for the next release) - applies a temporary fix for the 32bit pinctrl registers on the RK3288
2019-03-29mmc: correct the HS400 initialization processBOUGH CHEN
After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed() which indicates that the HS200/HS400 to HS downgrade is happening. During the HS400 initialization, first select to HS200, and config the related clock rate, then downgrade to HS mode. So here also need to config the downgrade value to be true for two reasons. First, make sure in the function mmc_set_card_speed(), after switch to HS mode, first config the clock rate, then read the EXT_CSD, avoid receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue the MMC_CMD_SWITCH command, it need to wait a bit then switch bus properties. Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer mode in this case, and USDHC will never get data transfer complete status, cause the uboot hang. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2019-03-29pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrlDavid Wu
There are no higher 16 writing corresponding bits for pmu_gpio0's iomux/drive/pull at rk3288, need to read the value from register firstly. Add the flag to distinguish it from normal registers. Signed-off-by: David Wu <david.wu@rock-chips.com>
2019-03-28sunxi: video: HDMI: Fix clock setupJernej Skrabec
Currently, HDMI driver doesn't consider minimum and maximum allowed rate of pll3 (video PLL). It works most of the time, but not always. Consider monitor with resolution 1920x1200, which has pixel clock rate of 154 MHz. Current code would determine that pll3 rate has to be set to 154 MHz. However, minimum supported rate is 192 MHz. In this case video output just won't work. The reason why the driver is written in the way it is, is that at the time HDMI PHY and clock configuration wasn't fully understood. But now we have needed knowledge, so the issue can be fixed. With this fix, clock configuration routine uses full range (1-16) for clock divider instead of limited one (1, 2, 4, 11). It also considers minimum and maximum allowed rate for pll3. Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-26Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Various fixes for bugs found by u-boot test.py
2019-03-25Convert CONFIG_SF_DEFAULT_* to KconfigPatrick Delaunay
This converts the following to Kconfig: CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_MODE CONFIG_SF_DEFAULT_SPEED I use moveconfig script and then manual check on generated u-boot.cfg to solve the remaining issue. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IPMarek Vasut
On 16bit variants of the TMIO SD IP, the SECCNT register can only be programmed to 16bit values, while on the 32bit and 64bit variants it can be programmed to 32bit values. The SECCNT register indicates the maximum number of blocks in a continuous transfer. Hence, limit the maximum continuous transfer block count to 65535 blocks on 16bit variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit variants. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-03-25mmc: sh_mmcif: Set default MMCIF clock rateMarek Vasut
Set MMCIF clock rate to 97.5 MHz, which is the default according to Gen2 datasheet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-03-25clk: renesas: Add support for setting MMCIF clock divider on Gen2Marek Vasut
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms. This allows the MMCIF driver to set higher clock rate if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Fix swapped div and mul in debug output on Gen2Marek Vasut
The $div and $mul values were swapped in the debug output, fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25clk: renesas: Fix SDH clock divider decoding on Gen2Marek Vasut
The gen2_clk_get_sdh_div() function is supposed to look up the $val value read out of the SDCKCR register in the supplied table and return the matching divider value. The current implementation was matching the value from SDCKCR on the divider value in the table, which is wrong. Fix this and rework the function a bit to make it more readable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25mmc: Align MMC_TRACE with tiny printfMarek Vasut
The tiny printf implementation only supports %x format specifier, it does not support %X . Since it makes little difference whether the debug output prints hex numbers in capitals or not, change it to %x and make the MMC_TRACE output work with tiny printf too. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org>
2019-03-21Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini
- i2c: i2c_cdns: Fix below warnings with checker tool
2019-03-21i2c: i2c_cdns: Fix below warnings with checker toolSiva Durga Prasad Paladugu
This patch fixes below warnings found with checker tool. The variable len in i2c_msg struct is of unsigned type and it is received as recv_count which is unsigned type but it is checked with < 0 which is always false, hence removed it. The local variable curr_recv_count is declared as signed type and compared aginst unsigned recv_count which is incorrect. This is fixed by declaring it as unsigned type. drivers/i2c/i2c-cdns.c: In function ‘cdns_i2c_read_data’: drivers/i2c/i2c-cdns.c:317:18: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if ((recv_count < 0)) ^ drivers/i2c/i2c-cdns.c:340:24: warning: comparison of integer expressions of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare] updatetx = recv_count > curr_recv_count; ^ drivers/i2c/i2c-cdns.c:361:39: warning: comparison of integer expressions of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare] while (readl(&regs->transfer_size) != Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-19Merge git://git.denx.de/u-boot-marvellTom Rini
- Enable network interface on clearfog_gt_8k (Baruch) - Fix dreamplug boot by adding an spi0 alias to the DT (Chris) - Fix / enhance Marvell ddr3 setup / parameters (Chris) - Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris) - Enable SPL_FLASH_BAR on db-88f6820-amc (Chris) - Use correct pcie controller name in Armada-38x dts files (Chris) - Disable d-cache on Kirkwood platforms as currently needed (Chris) - Add a more descriptive comment to pci_mvebu.c (Stefan) - Update Marvell maintainers entry (Stefan)