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2019-05-23stm32mp1: ram: add tuning in DDR interactive modePatrick Delaunay
Add command tuning for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to execute software tuning for the DDR configuration: - software read DQS Gating (replace the built-in one) - Bit de-skew - Eye Training or DQS training Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: add tests in DDR interactive modePatrick Delaunay
Add command tests for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to verify the DDR configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: add interactive mode for DDR configurationPatrick Delaunay
This debug mode is used by CubeMX DDR tuning tools or manualy for tests during board bring-up. It is simple console used to change DDR parameters and check initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: add support for LPDDR2/LPDDR3Patrick Delaunay
Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: update parameter array initializationPatrick Delaunay
Force alignment of the size of parameters array with the expected value in the binding, that allows compilation error when the array size change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: change ddr speed to kHzPatrick Delaunay
Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: increase the delay after reset to 128 cyclesPatrick Delaunay
Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23stm32mp1: ram: update mask for operating modePatrick Delaunay
Regression introduced by rebase, when loop was replaced by readl_poll_timeout() function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23serial: stm32: remove watchog reset in debug putcPatrick Delaunay
For STM32MP, the watchdog is based on DM and the function watchod_reset call the function uclass_get_device(UCLASS_WDT) to found the driver associated IWDG2. As this reset is not mandatory in debug putc (the uart fifo will be empty after some us), we can simplify the code by removing this call. And this patch avoid issue when putc is called before initialization of DM core, before the parsing of the device tree parsing and each node bound to driver; that also avoid memory leak. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23serial: stm32: remove unnecessary tracePatrick Delaunay
Remove the trace indicating the end of the DEBUG initialization Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23clk: stm32mp1: add set_rate for DDRPHYC clockPatrick Delaunay
Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23i2c: stm32f7: improve loopback in timing algorithmNicolas Le Bayon
This avoids useless loops inside the I2C timing algorithm. Actually, we support only one possible solution per prescaler value. So after finding a solution with a prescaler, the algorithm can switch directly to the next prescaler value. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23i2c: stm32f7: Fix SDADEL minimum formulaNicolas Le Bayon
It conforms with Reference Manual I2C timing section. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPCYinbo Zhu
PowerPC supports 32 bit address. So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-23driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPCYinbo Zhu
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22Merge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dmTom Rini
Various DM fixes Addition of ofnode_get_addr_size_index()
2019-05-22driver: watchdog: add sp805 watchdog supportQiang Zhao
sp805 is watchdog on some NXP layerscape SoCs, adding it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT needs to be enabled to use it. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22scsi: ceva: Clean up the driver codePeng Ma
Distinguish the ecc val by chassis version and move the ecc addr to dts. Add ls1028a soc support. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21dm: core: Fix dm_extended_scan_fdt()Patrice Chotard
This function takes an argument, blob, but never uses it, instead uses gd->fdt_blob directly. Fixes: e81c98649b7a ("dm: core: add clocks node scan") Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-21core: ofnode: Have ofnode_read_u32_default return a u32Trent Piepho
It was returning an int, which doesn't work if the u32 it is reading, or the default value, will overflow a signed int. While it could be made to work, when using a C standard/compiler where casting negative signed values to unsigned has a defined behavior, combined with careful casting, it seems obvious one is meant to use ofnode_read_s32_default() with signed values. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com>
2019-05-21core: ofnode: Add ofnode_get_addr_size_indexKeerthy
Add ofnode_get_addr_size_index function to fetch the address and size of the reg space based on index. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-21spl: misc: Allow misc drivers in SPL and TPLSimon Glass
In some cases it is necessary to read the keyboard in early phases of U-Boot. The cros_ec keyboard is kept in the misc directory. Update the config to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-05-21mmc: tmio: sdhi: HS400 manual adjustmentMarek Vasut
Since Gen3 SDHI has an internal DS signal AC-spec violation in HS400 mode, CRC-error may occur in read command in HS400 mode. This phoenomenon occurs at low/high temperature. To fix this, after completion of HS400 tuning, enable manual calibration. However, Gen3 M3 Ver.1.2 or earlier and H3 1.x does not support HS400. These SoC forcibly use HS200 mode by SoC attribute. The DT adjustment of the tuning parameters is not supported until the DT property names become clear. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Adapted from a patch by Takeshi Saito <takeshi.saito.xv@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21mmc: tmio: sdhi: Minor macro cleanupMarek Vasut
Clean up the whitespaces in macros, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21pci: renesas: Add RCar Gen3 PCIe controller driverMarek Vasut
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs. The PCIe on Gen3 is used both to connect external PCIe peripherals. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21Merge git://git.denx.de/u-boot-mpc83xxTom Rini
- Update MPC83xx platform support to current best practices, etc.
2019-05-21Merge tag 'mmc-5-20' of https://github.com/MrVan/u-bootTom Rini
"Please pull mmc-5-20 for v2019.07, this is to avoid break i.MX53 boot."
2019-05-21Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-videoTom Rini
- update for using splashfile instead of location->name when loading the splash image from a FIT - updates for loading internal and external splash data from FIT - DM_GPIO/DM_VIDEO migration for mx53 cx9020 board - fix boot issue on mx6sabresd board after DM_VIDEO migration - increase the max preallocated framebuffer BPP to 32 in ipuv3 driver to prepare for configurations with higher color depth - allow to use vidconsole_put_string() in board code for text output on LCD displays
2019-05-21board: gazerbeam: Fix SC detectionMario Six
The single channel detection in the gazerbeam board driver was not implemented correctly. Fix the detection. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys_rxaui_ctrl: Use new regmap interfaceMario Six
For the DM case, use the proper parameter for the regmap_init_mem call (which is the ofnode, not the udevice). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys_rxaui_ctrl: Return old stateMario Six
Make the gdsys_rxaui_ctrl polarity setting function return the old state to comply with the API requirements. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21i2c: ihs: Improve error handlingMario Six
Improve the error handling and reporting of the IHS I2C driver. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-05-21i2c: ihs: Get rid of fpgamapMario Six
Since the IHS I2C driver want upstream, the surrounding infrastructure has changed quite a bit (notably, the fpgamap driver was replaced with a regmap driver). Update the driver to work with these changes. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-05-21mpc83xx_clk: Add enable methodMario Six
Some DM drivers have hardcoded clk_enable calls when handling clocks (for example the fsl_esdhc driver). To work with these drivers, add an enable method to the MCP83xx clock driver (which does nothing, because the clocks are always enabled). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to KconfigMario Six
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Make distinct caddy2 configMario Six
vme8349.h contains two separate boards: The vme8349 itself, and the caddy2 board. The caddy2 board is chosen by setting certain config variables. Create a proper config file for the caddy2 board to make Kconfig migration easier. Furthermore, simplify the vme8349 and caddy2 configs by keeping only the options necessary for each board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20vme8349: Migrate to CONFIG_TARGET_VME8349Mario Six
CONFIG_TARGET_VME8349 can replace CONFIG_VME8349. Hence, replace CONFIG_VME8349 with CONFIG_TARGET_VME8349, and remove CONFIG_VME8349. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC837XMario Six
Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC836*Mario Six
Replace CONFIG_MPC836* with proper CONFIG_ARCH_MPC836* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC834*Mario Six
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC831*Mario Six
Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20mpc83xx: Introduce ARCH_MPC830*Mario Six
Replace CONFIG_MPC830* with proper CONFIG_ARCH_MPC830* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-20Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini
- Fix for mxc_i2c driver in DM mode, thanks to Trent!
2019-05-20video: Factor out vidconsole_put_string()Marek Vasut
Pull the vidconsole_put_string() function from DM tests, make it available to e.g. boards that want to display information on the LCD on boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-05-20video: ipuv3: Set max display bpp to 32Marek Vasut
The IPUv3 can handle 1920x1080x32bpp displays , set the max preallocated framebuffer BPP to 32 to cater for all eventualities. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
2019-05-20dm: arm: imx: video: add compatible for imx53-ipuSteffen Dirkwinkel
This code also works with imx53 ipus so we can enable it for them. Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
2019-05-20Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"Lukasz Majewski
This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which causes the imx53 HSC to hang as the eMMC is not working properly anymore. The exact error message: MMC write: dev # 0, block # 2, count 927 ... mmc write failed 0 blocks written: ERROR imx53 is not using the DDR mode. Debugging of pre_div and div generation showed that those values are generated in a way, which is not matching the ones from working setup. As the original patch was performing code refactoring, let's revert this change, so all imx53 boards would work again. Signed-off-by: Lukasz Majewski <lukma@denx.de>
generated by cgit (git 2.34.1) at 2025-02-05 11:47:32 +0000