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2018-04-06drivers: serial: remove nonexisting initialisation functionsChristophe Leroy
This patch removes call of serial initialisation functions that are not implemented anymore. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06Migrate CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSCAlex Kiernan
This converts CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC to Kconfig Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-06powerpc: mpc8xx: move watchdog into drivers/watchdogChristophe Leroy
In preparation of DM watchdog, move basic actions into drivers/watchdog Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06powercp: mpc8xx: move commproc.hChristophe Leroy
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and move it into arch/powerpc/include/asm Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xxChristophe Leroy
CONFIG_8xx doesn't mean much outside of arch/powerpc/ This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ... It also renames 8xx_immap.h to immap_8xx.h to be consistent with other file names. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06soft_i2c: cleanup - no mpc8xx supportChristophe Leroy
commit 907208c452999 ("powerpc: Partialy restore core of mpc8xx") didn't bring back support for I2C on the mpc8xx Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06spi: atmel: default y if DM_SPI && ARCH_AT91Jagan Teki
ATMEL_SPI is now fully converted to driver-model and respective boards switch to DM_SPI as well, so make default y for ARCH_AT91 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06spi: atmel: Drop atmel_spi.hJagan Teki
atmel_spi.h has register offsets, and atmel_spi_slave structure, move it into .c file for better readability and drop atmel_spi.h Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06spi: atmel: Drop non-dm codeJagan Teki
All board configs are now enabled DM_SPI for SPL and U-Boot proper, so now its time to drop non-dm code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06spi: atmel: Add ifdef for DM_GPIO codeJagan Teki
Few boards are configuring gpio directly from board instead using drivers/gpio so add ifdef for DM_GPIO to compatible for both the cases. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06Merge tag 'signed-rpi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for rpi - 2018-04-06 Highlights this time around: - Support for new RPi3 B+ model - Fix for some SD cards on newer RPi firmware
2018-04-05mmc: use core clock frequency in bcm2835 sdhostJonathan Gray
In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and later start.elf now sets the EMMC clock to 200 MHz. According to Phil Elwell in https://github.com/raspberrypi/firmware/issues/953 the SDHost controller shares the core/VPU clock and doesn't use the EMMC clock. Use the core clock id when determining the frequency to allow U-Boot to work with recent versions of raspberrypi-firmware. Otherwise U-Boot hangs at: U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100) DRAM: 948 MiB RPI 3 Model B (0xa02082) MMC: mmc@7e202000: 0, sdhci@7e300000: 1 Loading Environment from FAT... Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-04Merge git://git.denx.de/u-boot-sunxiTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-04sunxi: revert disabling of featuresAndre Przywara
In January some commits were introduced to mitigate the U-Boot image size issues we encountered on sunxi builds. Now with the MMC environment removed we can bring them back, as we practically don't have a size limit anymore. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04net: sun8i-emac: remove support for old bindingAndre Przywara
The original DT binding used by U-Boot's sun8i-emac driver was not really agreed upon, and deviated from the "official" binding now used by the kernel. Since now all U-Boot users have been converted to the new binding, we can remove support for the old DT nodes from the driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04net: sun8i-emac: add support for new EMAC DT bindingAndre Przywara
The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) got an upstream Linux driver in v4.15. This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when the node, which phy-handle points to, is a child node of an "allwinner,sun8i-h3-mdio-internal" node. Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding for now, to allow a smooth transition. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04net: sun8i-emac: support new pinctrl DT bindingsAndre Przywara
The Linux kernel driver for the Allwinner pin controller gained support for generic properties, which are now also used in the DTs. The sun8i-emac Ethernet driver for new Allwinner MACs reads the pins from the DT, but so far only supported the old binding. Update the parsing routine to cope with both the old and new bindings, so that the newer DTs can be used with U-Boot and its Ethernet driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-04sunxi: gpio: add missing compatible stringsAndre Przywara
The sunxi GPIO driver is missing some compatible strings for recent SoCs. While most of the sunxi GPIO code seems to not rely on this (and so works anyway), the sunxi_name_to_gpio() function does and fails at the moment (for instance when resolving the MMC CD pin name). Add the compatible strings for the A64 and V3s, which were missing from the list. This now covers all pinctrl nodes in our own DTs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-03sunxi: move the NAND parameters to KconfigMiquel Raynal
Move the NAND parameters from defconfig files to Kconfig for SUNXI architecture only. Fort now only the CHIP pro is migrated. It would have been better to convert this defconfig entry to Kconfig for all supported machines/architectures but it has been abandoned due to a fairly high amount of errors reported by the moveconfig.py tool. This is due to defines quite often being multiplications of values/other defines not correctly handled. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03sunxi: make NAND_SUNXI use ARCH_SUNXI as default in KconfigMiquel Raynal
Remove NAND_SUNXI from the CHIP pro defconfig to be automatically selected depending on the state of ARCH_SUNXI. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03sunxi: automatically select SPL_NAND_SUPPORT in KconfigMiquel Raynal
Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the number of entries to add in defconfig files when adding NAND support. For now, the only board using it is the CHIP pro. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03sunxi: allow NAND support to be compiled for sun8i platformsMiquel Raynal
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I in Kconfig. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: use PIO instead of DMAMiquel Raynal
SPL support was first written to support only the earlier generations of Allwinner SoCs, and was only really enabled on the A13 / GR8. However, those old SoCs had a DMA engine that has been replaced since the A31 by another DMA controller that is no longer compatible. Since the code directly uses that DMA controller, it cannot operate properly on the later SoCs, while the NAND controller has not changed. There's two paths forward, the first one would have been to add support for that DMA controller too, the second to just remove the DMA usage entirely and rely on PIO. The later has been chosen because CPU overload at this stage is not an issue and it makes the driver more generic, and easier to understand. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: declare the ecc_bytes array globallyMiquel Raynal
Move the ecc_bytes array out of nand_max_ecc_strength() for future use by nand_read_page(). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: make the reset column helper more genericMiquel Raynal
Prepare the future use of an helper to move the data pointer (the column) of the NAND chip by renaming nand_reset_column() to nand_change_column(). Resetting the column is just a matter of giving 0 as argument. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: ensure enough time has passed after changing the columnMiquel Raynal
When changing the column, the ONFI specification states that a minimum time of tCCS (Change Column Setup time) must elapse between the last address cycle is asserted on the bus and the first data cycle is clocked. An usual value for average NANDs is 500 nanoseconds. Round it up to 1 microsecond to be safe. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: create an helper to handle command executionMiquel Raynal
Executing a command is matter of always doing the following sequence: * Waiting for the FIFO to be empty so we can fill it with the new command. * Clearing the status register. * Writing the command in the FIFO. * Waiting for the command to finish. Add a nand_exec_cmd() helper to handle this instead of repeating the logic through the various functions. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: add missing status clearMiquel Raynal
It is best practice to always clear the status register before executing a command to be sure that the status read afterwards is relevant. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helperMiquel Raynal
One bit in the control registers indicates if the NAND controller is ready to receive a new command. Otherwise, the command FIFO is full and we should wait for this bit to flip. It then states that the last command has been processed and the FIFO is now free to welcome another command. Add this sanity check before starting any new command. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: introduce the nand_wait_int() helperMiquel Raynal
The pattern of polling on a status register until a bit is set or a timeout occurs is repeated multiple times in the driver. Mutualize the code by introducing the nand_wait_int() helper that does wait for the bit to flip or returns an error in case of timeout. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: fix typo on register nameMiquel Raynal
Change NFC_SEND_ADR to NFC_SEND_ADDR. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03spl: nand: sunxi: fix second case of modulo by zero errorMiquel Raynal
In the nand_read_buffer() step, the seed is calculated by doing a modulo by conf->nseeds which is always zero when not using the randomizer (most of SLC NANDs). This situation turns out to lead to a run time freeze with certain toolchains. Derive this seed only when the randomizer is enabled (and conf->nseeds logically not zero), exactly like what has been done before with an identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo by zero error"). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-03mtd: nand: sunxi: fix ECC strength choiceMiquel Raynal
When the requested ECC strength does not exactly match the strengths supported by the ECC engine, the driver is selecting the closest strength meeting the 'selected_strength > requested_strength' constraint. Fix the fact that, in this particular case, ecc->strength value was not updated to match the 'selected_strength'. For instance, one can encounter this issue when no ECC requirement is filled in the device tree while the NAND chip minimum requirement is not a strength/step_size combo natively supported by the ECC engine. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-04-01Merge git://git.denx.de/u-boot-dmTom Rini
2018-04-01core: ofnode: Fix translation for #size-cells == 0Mario Six
Commit 286ede6 ("drivers: core: Add translation in live tree case") made dev_get_addr always use proper bus translations for addresses read from the device tree. But this leads to problems with certain busses, e.g. I2C busses, which run into an error during translation, and hence stop working. It turns out that of_translate_address() and fdt_translate_address() stop the address translation with an error when they're asked to translate addresses for busses where #size-cells == 0 (comment from drivers/core/of_addr.c): * Note: We consider that crossing any level with #size-cells == 0 to mean * that translation is impossible (that is we are not dealing with a value * that can be mapped to a cpu physical address). This is not really specified * that way, but this is traditionally the way IBM at least do things To fix this case, we check in both the live-tree and non-live tree-case, whether the bus of the device whose address is about to be translated has size-cell size zero. If this is the case, we just read the address as a plain integer and return it, and only apply bus translations if the size-cell size if greater than zero. Signed-off-by: Mario Six <mario.six@gdsys.cc> Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Reported-by: Martin Fuzzey <mfuzzey@parkeon.com> Fixes: 286ede6 ("drivers: core: Add translation in live tree case") Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-01dm: core: make fixed-clock dt scan live dt compatibleAndy Yan
dm_scan_fdt_node can't work when live dt is active, we should use dm_scan_fdt_live instead. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-31pinctrl-uclass: convert to use live dtKever Yang
Use live dt interface for pinctrl_select_state_full() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-31core: add uclass_get_device_by_phandle_id() apiKever Yang
Add api for who can not get phandle from a device property. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-30Merge git://git.denx.de/u-boot-marvellTom Rini
2018-03-30Merge git://git.denx.de/u-boot-x86Tom Rini
2018-03-30Merge git://git.denx.de/u-boot-riscvTom Rini
2018-03-30arm64: a37xx: pci: add support for aardvark pcie driverWilson Ding
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: Wilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725 Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Correct mpp definitionsKen Ma
This patch corrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/43288 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Fix gpio pin offset in registerKen Ma
For armada_37xx_update_reg(), the parameter offset should be pointer so that it can be updated, otherwise offset will keep old value, and then when offset is larger than or equal to 32 the mask calculated by "BIT(offset)" will be 0 in gpio chip hook functions, it's an error, this patch set offset parameter of armada_37xx_update_reg() as pointer. Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Fix the pin 23 on south bridgeKen Ma
Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible when the gpio regulator used the gpio 23, the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Reviewed-on: http://vgitil04.il.marvell.com:8080/43284 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30arm64: a37xx: pinctrl: Fix number of pin in south bridgeKen Ma
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and not 29). Reviewed-on: http://vgitil04.il.marvell.com:8080/43285 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30dm: pcie: designware: add correct ATU handlingIgal Liberman
Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-03-30x86: mmc: Fix mapping of BAR memoryBernhard Messerklinger
Use dm_pci_map_bar function for BAR mapping. This has the advantage of clearing BAR flags and and only accepting mapped memory. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-03-30dm: pci: Avoid setting a PCI region that has 0 sizeBin Meng
It makes no sense to set a PCI region that has 0 size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30dm: pci: Check board information pointer in decode_regions()Bin Meng
PCI enumeration may happen very early on an x86 board. The board information pointer should have been checked in decode_regions() as its space may not be allocated yet. With this commit, Intel Galileo board boots again. Fixes: 664758c ("pci: Fix decode regions for memory banks") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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