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2017-11-29mtd: nand: introduce NAND_ROW_ADDR_3 flagMasahiro Yamada
Several drivers check ->chipsize to see if the third row address cycle is needed. Instead of embedding magic sizes such as 32MB, 128MB in drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since nand_scan_ident() knows well about the device, it can handle this properly. The flag is set if the row address bit width is greater than 16. Delete comments such as "One more address cycle for ..." because intention is now clear enough from the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wenyou Yang <wenyou.yang@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
2017-11-29mtd: nand: add generic helpers to check, match, maximize ECC settingsMasahiro Yamada
Driver are responsible for setting up ECC parameters correctly. Those include: - Check if ECC parameters specified (usually by DT) are valid - Meet the chip's ECC requirement - Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set The logic can be generalized by factoring out common code. This commit adds 3 helpers to the NAND framework: nand_check_ecc_caps - Check if preset step_size and strength are valid nand_match_ecc_req - Match the chip's requirement nand_maximize_ecc - Maximize the ECC strength To use the helpers above, a driver needs to provide: - Data array of supported ECC step size and strength - A hook that calculates ECC bytes from the combination of step_size and strength. By using those helpers, code duplication among drivers will be reduced. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 2c8f8afa7f92acb07641bf95b940d384ed1d0294]
2017-11-29mtd: nand: Pass the CS line to ->setup_data_interface()Boris Brezillon
Some NAND controllers can assign different NAND timings to different CS lines. Pass the CS line information to ->setup_data_interface() so that the NAND controller driver knows which CS line is concerned by the setup_data_interface() request. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 104e442a67cfba4d0cc982384761befb917fb6a1] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: allow drivers to request minimum alignment for passed bufferMasahiro Yamada
In some cases, nand_do_{read,write}_ops is passed with unaligned ops->datbuf. Drivers using DMA will be unhappy about unaligned buffer. The new struct member, buf_align, represents the minimum alignment the driver require for the buffer. If the buffer passed from the upper MTD layer does not have enough alignment, nand_do_*_ops will use bufpoi. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 477544c62a84d3bacd9f90ba75ffc16c04d78071]
2017-11-29mtd: nand: Wait for PAGEPROG to finish in drivers setting ↵Boris Brezillon
NAND_ECC_CUSTOM_PAGE_ACCESS Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the full read/write page sequence, and waiting for a page to actually be programmed is part of this write-page sequence. This is also what is done in ->write_oob_xxx() hooks, so let's do that in ->write_page_xxx() as well to make it consistent. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 41145649f4acb30249b636b945053db50c9331c5] [masahiro: There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot. No driver is affected by this change.] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Drop the ->errstat() hookBoris Brezillon
The ->errstat() hook is no longer implemented NAND controller drivers. Get rid of it before someone starts abusing it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 7d135bcced20be2b50128432c5426a7278ec4f6d] [masahiro: modify davinci_nand.c for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Drop unused cached programming supportBoris Brezillon
Cached programming is always skipped, so drop the associated code until we decide to really support it. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 0b4773fd1649e0d418275557723a7ef54f769dc9] [masahiro: modify davinci_nand.c for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: add mtd_ooblayout_xxx() helper functionsBoris Brezillon
In order to make the ecclayout definition completely dynamic we need to rework the way the OOB layout are defined and iterated. Create a few mtd_ooblayout_xxx() helpers to ease OOB bytes manipulation and hide ecclayout internals to their users. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 75eb2cec251fda33c9bb716ecc372819abb9278a] [masahiro: cherry-pick more code from adbbc3bc827eb1f43a932d783f09ba55c8ec8379] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Support controllers with custom pageMarc Gonzalez
If your controller already sends the required NAND commands when reading or writing a page, then the framework is not supposed to send READ0 and SEQIN/PAGEPROG respectively. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 3371d663bb4579f1b2003a92162edd6d90edd089] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Add a few more timings to nand_sdr_timingsBoris Brezillon
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the nand_sdr_timings struct. Assign default/safe values for the statically defined timings, and extract them from the ONFI parameter table if the NAND is ONFI compliant. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [Linux commit: 204e7ecd47e26cc12d9e8e8a7e7a2eeb9573f0ba Fixup commit: 6d29231000bbe0fb9e4893a9c68151ffdd3b5469] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Fix data interface configuration logicBoris Brezillon
When changing from one data interface setting to another, one has to ensure a specific sequence which is described in the ONFI spec. One of these constraints is that the CE line has go high after a reset before a command can be sent with the new data interface setting, which is not guaranteed by the current implementation. Rework the nand_reset() function and all the call sites to make sure the CE line is asserted and released when required. Also make sure to actually apply the new data interface setting on the first die. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: d8e725dd8311 ("mtd: nand: automate NAND timings selection") Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [Linux commit: 73f907fd5fa56b0066d199bdd7126bbd04f6cd7b] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: automate NAND timings selectionBoris Brezillon
The NAND framework provides several helpers to query timing modes supported by a NAND chip, but this implies that all NAND controller drivers have to implement the same timings selection dance. Also currently NAND devices can be resetted at arbitrary places which also resets the timing for ONFI chips to timing mode 0. Provide a common logic to select the best timings based on ONFI or ->onfi_timing_mode_default information. Hook this into nand_reset() to make sure the new timing is applied each time during a reset. NAND controller willing to support timings adjustment should just implement the ->setup_data_interface() method. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [Linux commit: d8e725dd831186a3595036b2b1df9f68cbc6efa3] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Expose data interface for ONFI mode 0Sascha Hauer
The nand layer will need ONFI mode 0 to use it as timing mode before and right after reset. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 6e1f9708dbf3c50a8da93c1952a01a7a2acb5e66] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: convert ONFI mode into data interfaceSascha Hauer
struct nand_data_interface is the designated type to pass to the NAND drivers to configure the timing. To simplify further patches convert the onfi_sdr_timings array from type struct nand_sdr_timings nand_data_interface. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: b1dd3ca203fccd111926c3f6ac59bf903ec62b05] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Create a NAND reset functionSascha Hauer
When NAND devices are resetted some initialization may have to be done, like for example they have to be configured for the timing mode that shall be used. To get a common place where this initialization can be implemented create a nand_reset() function. This currently only issues a NAND_CMD_RESET to the NAND device. The places issuing this command manually are replaced with a call to nand_reset(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [Linux commit: 2f94abfe35b210e7711af9202a3dcfc9e779219a] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29mtd: nand: Add an option to maximize the ECC strengthBoris Brezillon
The generic NAND DT bindings allows one to tweak the ECC strength and step size to their need. It can be used to lower the ECC strength to match a bootloader/firmware config, but might also be used to get a better reliability. In the latter case, the user might want to use the maximum ECC strength without having to explicitly calculate the exact value (this value not only depends on the OOB size, but also on the NAND controller, and can be tricky to extract). Add a generic 'nand-ecc-maximize' DT property and the associated NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best ECC strength and step-size on their own. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82] [masahiro: of_property_read_bool -> fdt_getprop for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29bitops: collect BIT macros to include/linux/bitops.hMasahiro Yamada
Same macros are defined in various places. Collect them into include/linux/bitops.h like Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-27Merge git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-27pinctrl: imx6ul: Fix pinctrl data overlapped with DT areaJagan Teki
before relocation pinctrl data BSS is overlapping DT area, when .data is using uninitialized global variable, imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID to prevent BSS overlap Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Reported-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-11-26rockchip: pinctrl: rk3399: add support for I2C8Philipp Tomsich
The RK3399 has a total of 9 I2C controllers. To support these, the enum in periph.h is extended and the mapping from the IRQ numbers to the peripheral-ids is extended to ensure that pinctrl requests are passed through to the function configuring the I2C pins. For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using communication with the FAN53555 connected on I2C8. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-11-26rockchip: clk: rk3399: change extract_bits to bitfield_extractPhilipp Tomsich
The RK3399 clk driver still has a left-over use of extract_bits, which can be replaced by using bitfield_extract from include/bitfield.h. This rewrites the invocation to use the shared function. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-24ARC: HSDK: introduce CREG GPIO driverEugeniy Paltsev
The HSDK can manage some pins via CREG registers block. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-11-21rockchip: spi: the symbol for Hertz is HzHeinrich Schuchardt
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: clock: update sysreset driver bindingKever Yang
Using priv for new sysreset driver binding. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: sysreset: update Makefile to work with merged sysreset driverPhilipp Tomsich
After applying the merged sysreset driver, there are build failures due to an out-of-sync Makefile. This updates drivers/sysreset/Makefile to address these build failures. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21rockchip: sysreset: merge into one common driverKever Yang
Use a common driver for all Rockchip SOC instead of one for each SoC. Use driver_data for reg offset. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21thermal: ti-bandgap: Add support for temperature sensorFaiz Abbas
The dra7xx series of SOCs contain a temperature sensor and an associated analog-to-digital converter (ADC) which produces an output which is proportional to the SOC temperature. Add support for this temperature sensor. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-20omap3: spi: the symbol for Hertz is HzHeinrich Schuchardt
fix typo Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-20Merge git://git.denx.de/u-boot-ubiTom Rini
2017-11-20Merge git://git.denx.de/u-boot-i2cTom Rini
2017-11-20ubi: no NULL check needed before kmem_cache_destroyHeinrich Schuchardt
kmem_cache_destroy calls free which checks for NULL. Problem was indicated by coccinelle. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-20i2c: add Amlogic Meson driverBeniamino Galvani
Add a driver for the I2C controller available on Amlogic Meson SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-20rtc: add support for s35392aNandor Han
Add support for S35392A RTC. The driver supports both U-Boot driver models. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Heiko Schocher <hs@denx.de>
2017-11-20bootcount: add support for bootcounter on EXT filesystemIan Ray
Add support for bootcounter on an EXT filesystem. Sync configuration whitelist. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
2017-11-20pwm: imx: Enable PWM support on i.MX53Martyn Welch
Add missing parts for i.MX53 PWM support Acked-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2017-11-20imx: mxc_i2c: tweak the i2c transfer methodNandor Han
Tweak the i2c transfer to work for devices that want to read data without addressing a register. Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Acked-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2017-11-19Merge git://git.denx.de/u-boot-dmTom Rini
2017-11-17dm: pci: change bus number register setting compliant with LinuxMinghuan Lian
This patch is to change U-Boot PCI bus assignement compliant with Linux. It means each PCIe controller's bus number is 0, not the current maximum PCI bus number, when start to scan this controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-17serial: nulldev: Implement "pending" function to fix tstc return "true"Wilson Lee
In U-boot, serial_tstc was use to determine is there have a character in serial console that pending for read. If there is no "pending" function implemented in serial driver, the serial-uclass will return "true(1)" to indicate there have a character pending to read. Thus, read a character from nulldev serial will result in continuous getting -EAGAIN return which might lead system to hang. This commit is to fix a bug in nulldev serial which implement "pending" function in nulldev serial to always indicate there is no character in console that pending for read. Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Bin Meng <bmeng.cn@gmail.com>
2017-11-17clk: clk_stm32f7: fix PLL clock division factorPatrice Chotard
Fix clock division factor initialization for RCC_PLLCFGR registers. PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared, it's a forbidden value. So update RCC_PLLCFGR using clrsetbits_le32() to set only necessary bits fields. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17mmc: arm_pl180_mmci: add .getcd callbackPatrice Chotard
Add .getcd callback to check is MMC card is present Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17mmc: arm_pl180_mmci: add clock supportPatrice Chotard
Allow to get and enable MMC related clock Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17mmc: arm_pl180_mmci: add bus_width DT property supportPatrice Chotard
Allow to get "bus-width" property from device tree Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17mmc: arm_pl180_mmci: adapt driver to DM usagePatrice Chotard
Convert this driver to driver model. This driver is also used by VEXPRESS platforms which doesn't use driver model. Tested on STM32F746 and STM32F769 platforms. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17mmc: arm_pl180_mmci: update arm_pl180_mmci_init() prototypePatrice Chotard
Update arm_pl180_mmci_init() prototype by adding struct mmc** param. This is needed before converting this driver to driver model in order to use arm_pl180_mmci_init() in driver model and in none driver model implementation Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-11-17omap2: nand: Make NAND_OMAP_GPMC_PREFETCH defaultTom Rini
This option provides better performance and should really always be enabled. Make this be default y. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2017-11-17net: phy: Add Amlogic Meson GXL Internal PHY supportNeil Armstrong
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY. The PHY acts as a generic PHY but needs a slight configuration right before it's configuration. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-11-17pinctrl: meson: Add GXL SupportNeil Armstrong
Add the Amlogic Meson GXL pinctrl support based on the GXBB driver and the synchronized DTS from Linux 4.13.5 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
2017-11-16dm: core: Correct address cast in dev_read_addr_ptr()Simon Glass
This currently causes a warning in sandbox and will not do the right thing: drivers/core/read.c: In function ‘dev_read_addr_ptr’: drivers/core/read.c:64:44: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr; Use map_sysmem() which is the correct way to convert an address to a pointer. Fixes: c131c8bca8 (dm: core: add dev_read_addr_ptr()) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-16Merge git://www.denx.de/git/u-boot-marvellTom Rini
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