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2019-02-01pinctrl: rockchip: Add common rockchip pinctrl driverDavid Wu
Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Add a sound driverSimon Glass
Add a sound driver for rk3288 supporting chromebook_jerry. This uses the I2S driver, and existing audio codec and the clock/pinmux support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Add an I2S driverSimon Glass
Add a driver for I2S which allows audio data to be sent from the SoC to the audio codec. The sample rate and other settings are hard-coded for now as there is no suitable device-tree binding available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass
Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-31Merge tag 'video-updates-for-2019.04-rc1' of git://git.denx.de/u-boot-videoTom Rini
- ihs and imx driver fixes - relax EDID validation checks for 0 hsync/vsync pulse width (support some quirky displays)
2019-01-31video: Add Meson Video Processing Unit DriverNeil Armstrong
This adds video output support for Amlogic GXBB/GXL/GXM chips. The supported ports are CVBS and HDMI (based on DW_HDMI). When using HDMI, only DMT modes are supported. There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB) Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> [narmstrong: fixed defines alignment in meson_canvas.c] Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31video: dw_hdmi: add support for color conversionJorge Ramirez-Ortiz
Some IPs like the meson VPU can only feed a particular pixel format to dw_hdmi. As of now, the driver is hardcoded to use RGB888 as input. This commit enables different pixel format inputs, with the appropriate CSC configuration. Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31video: dw_hdmi: support SoC specific read/write opsJorge Ramirez-Ortiz
Some IPs like the meson VPU have a specific way to write to dw_hdmi registers. Make it configurable. Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> [added commit description] Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31power: domain: meson-gx-pwrc-vpu: add missing dependsMaxime Jourdan
MESON_GX_VPU_POWER_DOMAIN should depend on POWER_DOMAIN. Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-30dfu: mmc: call fs functions instead of run_commandSimon Goldschmidt
This unbreaks dfu mmc_file_op which is currently broken since using the load cmd on a buffer from heap is not allowed - added with commit aa3c609e2be5 ("fs: prevent overwriting reserved memory") Fixes: commit aa3c609e2be5 ("fs: prevent overwriting reserved memory") Reported-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-30Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- Enable DM_MMC support
2019-01-30sunxi: clk: enable clk and reset for CCU devicesAndre Przywara
Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-30Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imxTom Rini
For 2019.04
2019-01-29mmc: sunxi: Honour non-removable property in DTAndre Przywara
If a board DT describes a cd-gpios property, but also marks the storage as non-removable, we must ignore the GPIO (as Linux does). Teach the DM_MMC part of the Allwinner MMC driver about the non-removable DT property, to fix DM_MMC access on the SoPine and Pine64-LTS board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29mmc: sunxi: Add DM clk and reset supportAndre Przywara
Now that we have the gate clocks and the reset gates in our new Allwinner clock driver, let's make use of them in the MMC driver, when DM_MMC is defined. We treat the reset device as optional now, as the older SoCs don't implement it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29mmc: sunxi: Add DM_MMC support for A80Jagan Teki
A80 gates clock already be part of CLK framework, so just add mod_clk offset with A80 compatible string. Cc: Rask Ingemann Lambertsen <rask@formelder.dk> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29mmc: sunxi: Add DM_MMC support for H6Jagan Teki
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset. Connect that with the respective compatible string. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29mmc: sunxi: Add remaining compatible stringsJagan Teki
Add MMC compatible strings for A83T, A64, H5. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29sunxi: clk: A80: add MMC clock supportAndre Przywara
The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29sunxi: clk: add MMC gates/resetsAndre Przywara
Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29pinctrl: meson: add pinconf supportJerome Brunet
Adding pinconf support is necessary to enable boot from SPI without breaking the eMMC. When booting from SPI, the ROM code leave pull downs on the eMMC pad. We need to set pinconf provided in DT to solve this Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
2019-01-28ihs_video_out: Fix error handlingMario Six
The ihs_video_out driver's error handling is incorrect in two places (one is a missing negation, and in one place a error should be ignored). Fix these two instances. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-28videomodes: Relax EDID validation checks for hsync/vsync pulse widthPriit Laes
Current EDID detailed timing parser errors out when either horizontal or vertical pulse sync width is 0, thus not allowing a display with EDID listed below work properly. EDID below works ok within Linux although it warns about these two fields being 0. Therefore relax the checks a bit so we can actually use this the screen out of the box. Of-course, this display itself is somewhat quirky display with following anti-features: - HPD pin is not usable - although resolution is 640x480, only top 240 pixels are visible $ xxd -p display.edid 00ffffffffffff0005a1e00301000000150f0103800f05780a0f6ea05748 9a2610474f200000010101010101010101010101010101012a08804520e0 0b1020004000953600000018000000fd0034441a2403000a202020202020 0000001000310a20202020202020202020200000001000002a4030701300 782d1100001e006b $ edid-decode display.edid EDID version: 1.3 Manufacturer: AMA Model 3e0 Serial Number 1 Digital display Maximum image size: 15 cm x 5 cm Gamma: 2.20 RGB color display First detailed timing is preferred timing Display x,y Chromaticity: Red: 0.6250, 0.3398 Green: 0.2841, 0.6044 Blue: 0.1494, 0.0644 White: 0.2802, 0.3105 Established timings supported: 640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz Standard timings supported: Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm 640 672 672 709 hborder 0 480 484 484 491 vborder 0 -hsync -vsync VertFreq: 60 Hz, HorFreq: 29478 Hz Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz Dummy block Dummy block Checksum: 0x6b (valid) Signed-off-by: Priit Laes <priit.laes@paf.com> Signed-off-by: Priit Laes <plaes@plaes.org>
2019-01-28mmc: fsl_esdhc: add compatible for fsl, imx53-esdhcPatrick Bruenn
Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms with CONFIG_DM_MMC=y Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-28MTD: nand: mxs_nand_spl: Fix empty function pointer for BBTAdam Ford
The initialization function calls a nand_chip.scan_bbt(mtd) but scan_bbt is never initialized resulting in an undefined function pointer. This will direct the function pointer to nand_default_bbt defined in the same file. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28spi: mxc_spi: Fix build warning on ARM64 platformsYe Li
When building mxc_spi driver on ARM64 platforms, get below build warnings. Fix it in this patch. In file included from include/common.h:48:0, from drivers/spi/mxc_spi.c:9: drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’: drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28pinctrl: imx: Fix select input issueYe Li
The pinctrl supports to set any bit in input register on iMX6 if the MSB of input value is 0xff. But the driver uses signed int for input value, so when executing the codes below, it won't meet. Because this is arithmetic right shift. if (input_val >> 24 == 0xff) Fix the issue by changing the input_val, config_val and mux_mode to u32. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28gpio: introduce CONFIG_SPL_DM_PCA953XPeng Fan
Introduce CONFIG_SPL_DM_PCA953X for SPL usage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28imx8: scu: use dedicated MU for SPLPeng Fan
SPL runs in EL3 mode, except MU0_A, others are not powered on, and could not be used. However normal U-Boot use MU1_A, so we could not reuse the one in dts. And we could not replace the one in dts with MU0_A, because MU0_A is reserved in secure world. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28Enable FEC driver to retrieve PHY address from device treeMartyn Welch
Currently if we have more than one phy on the MDIO bus, we do not have a good mechanism for determining which should be used at runtime. Enable the FEC driver to determine the address for the PHY from the device tree. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-26Merge branch '2019-01-25-master-imports'Tom Rini
- snapdragon 820c improvements - poplar updates - DFU + SPL cleanups - Improve the mediatek mmc driver - Other minor cleanups / improvements
2019-01-26misc: i2c_eeprom: Add atmel,24c08 to the listMichal Simek
Linux kernel binding is using atmel,24c08 compatible string. On the other hand there is atmel,24c08a which is not listed in the kernel. Add compatible string without "a" suffix to be compatible with Linux kernel binding. These eeproms are available on several ZynqMP development boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-26drivers: esdhc: add support for ColdFire mcf5441x familyAngelo Dureghello
This patch has been tested on the mcf54415-based stmark2 board. The eSDHC driver works reliably using DMA mode. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-01-26dfu: Make DFU support more SPL friendlyAndrew F. Davis
Do this by using $(SPL_) in Makefiles and CONFIG_IS_ENABLED in C code. This ensures the files and features are only built into the right build for which they are enabled. Using the macros to simplify this patch was made possible by the config symbol rename done in the last patch. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26spl: Kconfig: Drop the _SUPPORT postfix from SPL_DFUAndrew F. Davis
The symbol CONFIG_SPL_DFU_SUPPORT in SPL build has the same meaning as CONFIG_DFU in regular U-Boot. Drop the _SUPPORT to allow for cleaner use in code. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26mmc: mtk-sd: fix SPL compilation when GPIO=y and SPL_GPIO=nFabien Parent
It is not possible to link the SPL image when CONFIG_GPIO is enabled but CONFIG_SPL_GPIO is not. Use the IS_ENABLED macro instead to correctly check whether CONFIG_{SPL_}GPIO is enabled. This commit fixes the following errors: * undefined reference to `dm_gpio_get_value * undefined reference to `gpio_request_by_name' Signed-off-by: Fabien Parent <fparent@baylibre.com> [trini: Move guard to fix warning in msdc_ops_get_wp()] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26mmc: mtk-sd: fix possible incomplete read opsFabien Parent
The code is checking for incomplete read when it see the INT_XFER_COMPL flag, but it forget to first check whether there is anything left in the FIFO to copy to the RX buffer. This means that sometimes we will get errors because of erroneous incomplete read operation. This commit fixes the driver re-ordering the code so that we first check for data inside the RX fifo and only after check the status of the INT_XFER_COMPL flag. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-01-25mmc: hi6220_dw_mmc: add compatible for Poplar supportShawn Guo
It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC Hi3798CV200 to probe this mmc driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25Merge tag 'arc-fixes-for-2019.04-rc1' of git://git.denx.de/u-boot-arcTom Rini
A couple of trivial fixes and improvements for ARC Most notable are: * Move of ENV_SIZE/ENV_OFFSET to Kconfig * Fix with private structure allocation for arc_uart * Definition of CONFIG_SYS_CACHELINE_SIZE useful for building drivers
2019-01-25serial_arc: Allocate buffer for private dataAlexey Brodkin
Apparently we never allocated buffer for arc_serial_platdata which for some reason never caused problems when executed in nSIM. But in Qemu this causes expected problems. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2019-01-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2019-01-24net: phy: aquantia: Print information on configValentin-catalin Neacsu
Print information about Aquantia system interface and firmware loaded on the phy. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: aquantia: Enable autoneg when on USXGMIIValentin-catalin Neacsu
If System Interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: remove CONFIG_MCAST_TFTPChris Packham
No mainline board enables CONFIG_MCAST_TFTP and there have been compilation issues with the code for some time. Additionally, it has a potential buffer underrun issue (reported as a side note in CVE-2018-18439). Remove the multicast TFTP code but keep the driver API for the future addition of IPv6. Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: move ether_crc to tsec driverChris Packham
ether_crc was added to the core net code in commit 53a5c424bf86 ("multicast tftp: RFC2090") so that other drivers could use it. However the only current user of it is tsec.c so move it there. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: realtek: Add functions to read PHY's extended registersCarlo Caione
According to the datasheet to access the extended registers we have to: 1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Write the target Register Data 3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE Standard Registers) Hook the missing functions so that we can use the `mdio rx/wx` command to easily access the extended registers. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: macb: fix mapping of registersRamon Fried
Some architectures (MIPS) needs mapping to access IOMEM. Fix that. Fixes: f1dcc19b213d ("net: macb: Convert to driver model") Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvneta: Add GPIO configuration supportAditya Prayoga
This patch add GPIO configuration support in mvneta driver. Driver will handle PHY reset. GPIO pins should be set in device tree. Ported from mvpp2x [https://patchwork.ozlabs.org/patch/799654/] Initial discussion to port the changes into mvneta [https://patchwork.ozlabs.org/patch/1005765/] Signed-off-by: Aditya Prayoga <aditya@kobol.io> Tested-by: Dennis Gilmore <dgilmore@redhat.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvgbe: fallback phy-mode to GMIIChris Packham
Some existing device trees don't specify a phy-mode so fallback to GMII when a phy-mode is not provided. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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