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2018-05-18configs: Add DDR Kconfig support for Arria 10Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee
Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee
Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-05-18sandbox: Rewrite i2c_pmic_emul.c to support PMIC with 3 bytes transmissionLukasz Majewski
This change enables support for MC34708 PMIC in sandbox. Now we can emulate the I2C transfers larger than 1 byte. Notable changes for this driver: - From now on the register number is not equal to index in the buffer, which emulates the PMIC registers - The PMIC register's pool is now dynamically allocated up till 64 regs * 3 bytes each = 192 B Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18pmic: dm: Add support for MC34708 for PMIC DMLukasz Majewski
This patch adds support for MC34708 PMIC, to be used with driver model (DM). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18pmic: dm: Rewrite pmic_reg_{read|write|clrsetbits} to support 3 bytes ↵Lukasz Majewski
transmissions This commit provides support for transmissions larger than 1 byte for PMIC devices used with DM (e.g. MC34708 from NXP). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-18pmic: Add support for setting transmission length in uclass private dataLukasz Majewski
The struct uc_pmic_priv's trans_len field stores the number of types to be transmitted per PMIC transfer. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-17Merge git://www.denx.de/git/u-boot-marvellTom Rini
2018-05-17net: MVGBE don't automatically select PHYLIBChris Packham
When Kconfig support was added for MVGBE it included automatically selected PHYLIB support. But MVGBE does not need PHYLIB it will build fine without it. Commit ed52ea507f12 ("net: add Kconfig for MVGBE") should have been a no-op in terms of build size but because of the selecting PHYLIB the openrd configs increased in size. Remove the automatic selection of PHYLIB, boards that need it will have already enabled it in their config header file. Fixes: commit ed52ea507f12 ("net: add Kconfig for MVGBE") Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-16Merge git://git.denx.de/u-boot-dmTom Rini
2018-05-16pinctrl: do not set_state for device without valid ofnodeKever Yang
Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk which add by mmc_bind(), these device do not have/need set pinctrl state. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-15usb: composite convert __set_bit to generic_set_bitBryan O'Donoghue
Compiling the f_mass_storage driver for an x86 target results in a compilation error as set_bit and clear_bit are provided by bitops.h To address that situation we discussed on the list moving to genetic_set_bit() instead. Doing a quick grep for similar situations in drivers/usb shows that the composite device is using __set_bit(). This patch switches over to generic_set_bit to maintain consistency between the two gadget drivers. Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Lukasz Majewski <lukma@denx.de> Cc: Marek Vasut <marex@denx.de>
2018-05-15usb: f_mass_storage: Fix set_bit and clear_bit usageBryan O'Donoghue
Compiling the f_mass_storage driver for an x86 target results in a compilation error as set_bit and clear_bit are provided by bitops.h Looking at the provenance of the current u-boot code and the git change history in the kernel, it looks like we have a local copy of set_bit and clear_bit as a hold-over from porting the Linux driver into u-boot. These days __set_bit and __clear_bit are optionally provided by an arch and can be used as inputs to generic_bit_set and generic_bit_clear. This patch switches over to generic_set_bit and generic_clear_bit to accommodate. Tested on i.MX WaRP7 and Intel Edison Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Lukasz Majewski <lukma@denx.de> Cc: Marek Vasut <marex@denx.de>
2018-05-15ARM: mvebu: a38x: Add missing SPDX license identfierChris Packham
mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code. When imported into u-boot we need to add the appropriate SPDX tag and re-format it slightly. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-05-15Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini
2018-05-15pwm: sunxi: add support for PWM found on Allwinner A64Vasily Khoruzhick
This commit adds basic support for PWM found on Allwinner A64. It can be used for pwm_backlight driver (e.g. for Pinebook) Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-05-15video: dw_hdmi: fix HSYNC and VSYNC polarity settingsVasily Khoruzhick
Currently dw_hdmi configures HSYNC polarity using VSYNC setting from EDID and vice versa. Fix it, since it breaks displays where HSYNC and VSYNC polarity differs Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2018-05-15sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.Vasily Khoruzhick
HSYNC is bit 8, and VSYNC is bit 9. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2018-05-14mmc: sdhci: Check that ops are definedRamon Fried
The check is necessary to avoid NULL pointer dereference. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2018-05-14net: add Kconfig for MVGBEChris Packham
Add Kconfig for MVGBE and update boards to select this. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2018-05-14net: mvgbe: remove CONFIG_DOVEChris Packham
Nothing defines CONFIG_DOVE so remove the code that uses it. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-14rockchip: clk: rk3288: handle clk_enable requests for GMACJonathan Gray
Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975 (rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC) Ethernet no longer probes on RK3288. Add no-ops for GMAC clocks observed to be requested which match the clk_enable cases in RK3368 and RK3399. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-14phy: marvell: a3700: Fix compatible string for ehciMarek Behún
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci", but the code searched for "marvell,armada-3700-ehci". Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: use non-zero size for ddr scrubbingChris Packham
Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: restore support for setting timingChris Packham
This restores support for configuring the timing mode based on the ddr_topology. This was originally implemented in commit 90bcc3d38d2b ("driver/ddr: Add support for setting timing in hws_topology_map") but was removed as part of the upstream sync. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: sync ddr training code with upstreamChris Packham
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: remove some unused codeChris Packham
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the rest of the ddr/marvell/a38x code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham
Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite only being used in the serdes code. Move this definition to ctrl_pex.h where all the other PEX defines are. Also remove the duplicate definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in ctrl_pex.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14watchdog: Add support for Armada 37xx CPU watchdogMarek Behún
This adds support for the CPU watchdog found on Marvell Armada 37xx SoCs. There are 4 counters which can be set as CPU watchdog counters. This driver uses the second counter (ID 1, counting from 0) (Marvell's Linux also uses second counter by default). In the future it could be adapted to use other counters, with definition in the device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14net: mvneta: Fix fault when wrong device treeMarek Behún
The driver does not check id phy_connect failed (for example on wrong property name in device tree). In such a case a fault occurs and the CPU is restarted. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: core: Cosmetic fixesMarek Behún
Move the reg_set* functions into comphy.h as static inline functions. Change return type of get_*_string to const char *. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14clk: armada-37xx: Support soc_clk_dumpMarek Behún
Add support for the clk dump command on Armada 37xx. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequencyMarek Behún
Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14driver: clk: Add support for clocks on Armada 37xxMarek Behún
The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Save/restore selector reg in SGMII initMarek Behún
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use comphy_mux on Armada 37xx.Marek Behún
Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Fix SGMII cfg and stat register addressesMarek Behún
The register addresses on lanes 0 and 1 are switched, first comes 1 and then 0. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: mux: Support nontrivial node order in selector registerMarek Behún
Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. As far as I know, there is no driver for Armada 37xx comphy in the kernel. When such a driver comes, this will need to be rewritten to support the device tree bindings from the kernel. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: revise the USB3 comphy setting during power onzachary
This commit is based on commit d9899826 by zachary <zhangzg@marvell.com> from u-boot-marvell, see github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826 - According to design specification, the transmitter should be set to high impedence mode during electrical idle. Thus transmitter should detect RX at high impedence mode also, and delay is needed to accommodate high impedence off latency. Otherwise the USB3 will have detection issue that most of the time the USB3 device can not be detected at all, or be detected as USB2 device sometimes. Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1 Bit 6: set to 1 to let Tx detect Rx at HiZ mode Bit [3:4]: set to 2 to be delayed by 2 clock cycles Bit 0: set to 1 to set transmitter to high impedance mode during idle. - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2 (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed to select 0x1(3.5dB emphasize). Thus need to override what comes from the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register 0x181 and bit0 of register 0x180). - According to USB3 application note, need to update below comphy registers: Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1) Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF) Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Set USB3 RX wait depending on ref clockMarek Behún
According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Access USB3 register indirectly on lane 2Marek Behún
When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. This is the case of the Turris Mox board from CZ.NIC. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_setsMarek Behún
Create a special function for indirect register setting, reg_set_indirect, and use it instead of the two calls to reg_set. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use (!ret) instead of (ret == 0)Marek Behún
In U-Boot it is usually written this way. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use same timeout for all register pollingMarek Behún
The timeout is set to PLL_LOCK_TIMEOUT in every call to comphy_poll_reg. Remove this parameter from the function. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Don't create functional macro for each registerMarek Behún
Currently there is for each register special functional macro, ie: LANE_CFG1_ADDR(u) GLOB_CLK_SRC_LO_ADDR(u) ... where can be either PCIE or USB3. Change this to one function PHY_ADDR(unit, addr). The code becomes: phy_addr(PCIE, LANE_CFG1) phy_addr(PCIE, GLOB_CLK_SRC_LO) ... Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Use reg_set16 instead of phy_write16Marek Behún
The macro phy_write16 is not used by the rest of the code, phy_read16 is not used at all. We also change the macro SGMIIPHY_ADDR to a static inline function. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-14phy: marvell: a3700: Change return type of macro MVEBU_REGMarek Behún
All the calls to reg_set and friends have to cast the first argument to void __iomem *. Lets change the return type of the MVEBU_REG macro instead. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-13mmc: Improve tinificationMarek Vasut
Drop all the extra content from the MMC core, so that tiny MMC support is really tiny, no fancy anything. That means the tiny MMC support does only 1-bit transfers at default speed settings. Moreover, this patch drops duplicate instance of struct mmc mmc_static, which wasted about 360 bytes. Furthermore, since MMC tiny supports only one controller at all times, get rid of mallocating the ext csd backup and replace it with static array. All in all, this patch saves ~4 kiB of bloat from the MMC core, which on platforms with severe limitations can be beneficial. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup checkpatch.pl style warnings] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-11Merge git://git.denx.de/u-boot-tegraTom Rini
generated by cgit (git 2.34.1) at 2024-12-29 14:05:17 +0000