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path: root/include/asm-ppc/immap_85xx.h
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2009-06-1285xx: Add PORBMSR and PORDEVSR shift definesPeter Tyser
Add defines similar to those already used for the the 86xx architecture. This will ease sharing of PCI code between the 85xx and 86xx architectures. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-1285xx: Add QE clk supportHaiying Wang
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <Timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12mpc85xx: USB: Add supportVivek Mahajan
The following patch adds 85xx-specific USB support and also revamps Copyright in immap_85xx.h Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-04-04eSPI: add the eSPI register supportMingkai Hu
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
2009-03-30MPC85xx: Add MPC8569 CPU supportHaiying Wang
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-09Add eTSEC 1/2 IO override control (corrected)ksi@koi8.net
This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.) Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
2009-02-1685xx: Add eSDHC support for 8536 DSAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16mpc85xx: Add support for the P2020Srikanth Srinivasan
Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-0485xx: Add PORDEVSR_PCI1 definePeter Tyser
Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-10-29Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-2785xx: Update MPC85xx_PORDEVSR_IO_SEL maskPeter Tyser
The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-2185xx: properly document MPC85xx_PORDEVSR2_SEC_CFGTimur Tabi
Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot to add a comment that the correct value disagrees with the 8544 reference manual. The changelog for that commit is also wrong, as it says "bit 28" when it should be "bit 24". Signed-off-by: Timur Tabi <timur@freescale.com>
2008-10-18Merge 'next' branchWolfgang Denk
Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-1785xx: Using proper I2C source clock divider for MPC8544Kumar Gala
The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being bit 26, instead it should be bit 28. This caused in incorrect interpretation of the i2c_clk which is the same as the SEC clk on MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported in PORDEVSR2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-07Fix the incorrect DDR clk freq reporting on 8536DSJason Jin
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-08-27mpc85xx: Add support for the MPC8536Kumar Gala
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-05-21Big white-space cleanup.Wolfgang Denk
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-2985xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala
All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-2985xx/86xx: Rename DDR init address and init extended address registerKumar Gala
Rename init_addr and init_ext_addr to match the docs between 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-18Fix calculation of I2C clock for some 85xx chipsTimur Tabi
Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and some use CCB/3. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Update immap_85xx.h to include the GUTS PORDEVSR2 register. Signed-off-by: Timur Tabi <timur@freescale.com>
2008-04-13Coding Style cleanup; update CHANGELOGWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-2685xx: Expand CCSR space with more DDR controller registers.James Yang
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Added support for multicore boot mechanismKumar Gala
Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Stop using immap_t on 85xxKumar Gala
In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Stop using immap_t for cpm offset on 85xxKumar Gala
In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Stop using immap_t for guts offset on 85xxKumar Gala
In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-08-16Fix numerous bugs in the 8568 UEC supportAndy Fleming
Actually, fixed a large bug in the UEC for *all* platforms. How did this ever work? uec_init() did not follow the spec for eth_init(), and returned 0 on success. Switch it to return the link like tsec_init() (and 0 on error) The immap for the 8568 was defined based on MPC8568, rather than CONFIG_MPC8568 CONFIG_QE was off CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is enabled Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14Add PCI support for MPC8568MDS boardHaiying Wang
This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
2007-08-148544ds PCIE supportEd Swarthout
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-07-11From: eran liberty <eran.liberty@gmail.com>Andy Fleming
adds the reset register to 85xx immap Signed-off-by: Eran Liberty <eran.liberty@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2006-10-20Use generic I2C register block on 85xx and 86xx.Jon Loeliger
Replace private IMMAP I2C structures with generic reg block and allow 86xx to have multiple I2C device busses. Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-08-09* Added support for initializing second PCI bus on 85xx Patch by Andy ↵Matthew McClintock
Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
2005-08-01Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger
- C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
2005-07-25* Patch by Jon Loeliger, 2005-05-05Jon Loeliger
Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
2005-07-23* Patch by Jon Loeliger, Kumar Gala 2005-02-08Jon Loeliger
- Convert the CPM2 based functionality to use new CONFIG_CPM2 option rather than a myriad of CONFIG_MPC8560-like variants. Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. Eliminates the CONFIG_MPC8560 option entirely. Distributes the new CONFIG_CPM2 option to each 8260 board.
2005-05-13Fix timer handling on MPC85xx systemswdenk
2004-10-10Patches by Jon Loeliger, 24 Aug 2004:wdenk
- Add support for the MPC8541 and MPC8555 CDS boards - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
2004-06-09Patches by Jon Loeliger, 11 May 2004:wdenk
(partially, as they contained a lot of crap)
2003-10-15* Patches by Xianghua Xiao, 15 Oct 2003:wdenk
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
generated by cgit (git 2.34.1) at 2024-12-27 09:34:26 +0000