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path: root/include/asm-ppc/processor.h
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2008-07-1485xx: Add some L1/L2 SPR register definitionsKumar Gala
Add new L1/L2 SPRs related to e500mc cache config and control. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips
Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-25mpc83xx: move CPU_TYPE_ENTRY over to processor.hKim Phillips
to avoid this: cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined In file included from cpu.c:33: /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-19Fix 4xx build issueAnatolij Gustschin
Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk
2008-06-1085xx: expose cpu identificationKumar Gala
The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-03ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson
This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-13ppc4xx: Add 405EX(r) revision C PVR definitions and detection codeStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-13ppc: Get rid of unused machine type definitionsWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-13Coding Style cleanup; update CHANGELOGWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26Update SVR numbers to expand supportAndy Fleming
FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-15ppc4xx: Add basic support for AMCC 460EX/460GT (3/5)Stefan Roese
This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-0985xx: Remove cache config from configs.hKumar Gala
Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-03Merge commit 'wd/master'Jon Loeliger
2007-10-31ppc4xx: Define CONFIG_BOOKE for all PPC440 based processorsEugene O'Brien
CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR number is used to access system registers. Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Add PPC405EX supportStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-17Initial mpc8610hpcd cpu/, README and include/ files.Jon Loeliger
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-1485xx start.S cleanup and exception supportAndy Fleming
From: Ed Swarthout <Ed.Swarthout@freescale.com> Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-10fsl_pci_init cleanup.Ed Swarthout
Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-10cpu/86xx fixes.Jon Loeliger
Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-27[PPC] Remove unused MSR_USER definitionRafal Jaworowski
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-07-19Fix breakage of 8xx boards from recent commit.Rafal Jaworowski
This patch fixes the negative consequences for 8xx of the recent "ppc4xx: Clean up 440 exceptions handling" commit. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-06-22Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk
2007-06-15ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki
- Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-05[PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot messageGrzegorz Wianecki
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2007-05-02Add support for the 8568 MDS boardAndy Fleming
This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23Enable 8544 supportAndy Fleming
* Add support to the Makefile * Add 8544 configuration support to the tsec driver * Add 8544 SVR numbers to processor.h Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-03-21[PATCH] Add AMCC PPC405EZ supportStefan Roese
This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-31[PATCH] Update 440EPx/440GRx cpu detectionStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-13[PATCH] Update 440SP(e) cpu revisionsStefan Roese
Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-28[PATCH] PPC4xx: 440SP Rev. C detection addedStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2006-09-19Merge branch 'master' of http://www.denx.de/git/u-bootJon Loeliger
Conflicts: board/stxxtc/Makefile
2006-09-14Merge branch 'mpc86xx'Jon Loeliger
2006-09-14Handle 86xx SVR values according to the new Reference Manual.Jon Loeliger
Both 8641 and 8641D have SVR == 0x8090, and are distinguished by the byte in bits 16-23 instead. Thanks to Jason Jin for noticing. Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-09-07Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
2006-08-22Merge branch 'mpc86xx'Jon Loeliger
2006-08-22Cleanup more poorly introduced whitespace.Jon Loeliger
2006-08-09Merge branch 'wd'Jon Loeliger
2006-07-03Cleanup config file and bootup output for Yucca board.Marian Balakowicz
2006-06-30Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz
2006-06-30Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz
2006-06-07Merge branch 'master' of http://www.denx.de/git/u-bootJon Loeliger
2006-05-10Add support for AMCC 440EP Rev C and 440GR Rev BStefan Roese
Patch by John Otken, 08 May 2006
2006-04-26Initial support for MPC8641 HPCN board.Jon Loeliger
2005-11-29Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.Stefan Roese
Patch by John Otken, 23 Nov 2005
2005-11-07Correct PPC Timebase register definitions (SPRN_TBRL...)Stefan Roese
Patch by Stefan Roese, 07 Nov 2005
2005-11-01Add support for Ocotea pass 3 with 440GX Rev. FStefan Roese
Patch by Stefan Roese, 01 Nov 2005
2005-10-04Fix 440GR to print correct cpu revisionStefan Roese
Patch by Stefan Roese, 4 Oct 2005
2005-09-23Cleanup (PPC4xx is AMCC now)Wolfgang Denk
2005-08-02Merge with rsync://git-user@source.denx.net/git/u-boot.gitJon Loeliger
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