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2009-07-17ppc: Fix compile error for boards with CONFIG_DDR_ECCPeter Tyser
A bug was introduced by commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC defined and resulted in errors such as: Configuring for canyonlands board... fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your processor" make[1]: *** No rule to make target `.depend', needed by `libdma.a'. Stop. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-07-16Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk
2009-07-16Merge branch 'asm-generic' of git://git.denx.de/u-boot-microblazeWolfgang Denk
2009-07-14usb: mpc834x: added support of the MPH USB controller in addition to the DR oneValeriy Glushkov
Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-07-14MPC512x: factor out common codeWolfgang Denk
Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
2009-07-14MPC512x: Add MSCAN1...4 Clock Control RegistersWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
2009-07-09asm-generic: Consolidate errno.h to asm-generic/errno.hMichal Simek
This patch use blackfin errno.h implementation which correspond Linux kernel one. MIPS implemetation is different that's why I keep it. I removed ppc_error_no.h from Marvell boards which was the same too. I have got ack from ppc40x, blackfin, arm, coldfire and avr custodians. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <monstr@monstr.eu>
2009-07-0283xx: Add support for fsl_dma driverPeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu> Tested-by: Ira W. Snyder <iws@ovro.caltech.edu> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-0285xx: Adds GPIO registers to MPC85xx Memory Map.Poonam Aggrwal
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01fsl_dma: Break out common memory initialization functionPeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01fsl_dma: Move dma function prototypes to common header filePeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01fsl_dma: Add bitfield definitions for common registersPeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-018xxx: Break out DMA code to a common filePeter Tyser
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-3086xx: Add CPU_TYPE_ENTRY supportKumar Gala
Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use this to convey the # of cores and DDR width in the near future so its good to keep in sync. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-1285xx: Add PORBMSR and PORDEVSR shift definesPeter Tyser
Add defines similar to those already used for the the 86xx architecture. This will ease sharing of PCI code between the 85xx and 86xx architectures. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12fsl/85xx, 86xx: Sync up DMA codePeter Tyser
The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12drivers/qe: Add more SNUM number for QEHaiying Wang
Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII- 1000 mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12drivers/qe: Change QE RISC ALLOCATION to support 4 RISCsHaiying Wang
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and define MAX_QE_RISC for QE based silicons. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-1285xx: Add QE clk supportHaiying Wang
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <Timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-1285xx: Added MPC8535/E identifiersKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12mcp512x: Add macros for SCFR LPC divisor accessStefan Roese
Thos macros will be used by the esd mecp5123 board. Signed-off-by: Stefan Roese <sr@denx.de>
2009-06-12mpc85xx: USB: Add supportVivek Mahajan
The following patch adds 85xx-specific USB support and also revamps Copyright in immap_85xx.h Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-06-12mpc83xx: USB: Reorganized its supportVivek Mahajan
The following patch reorganizes/reworks the USB support for mpc83xx as under:- * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to cpu/mpx83xx/cpu_init.c * Board specific usb_phy_type is read from the environment * Adds USB EHCI specific structure in include/usb/ehci-fsl.h * Copyrights revamped in most of the following files Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-06-1283xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser
Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-06-1283xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xxPeter Tyser
Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-06-12MPC512x: remove include/mpc512x.hWolfgang Denk
Move needed definitions (register descriptions etc.) from include/mpc512x.h into include/asm-ppc/immap_512x.h. Instead of using a #define'd register offset, use a function that provides the PATA controller's base address. All the rest of include/mpc512x.h are register offset definitions which can be eliminated by proper use of C structures. There are only a few register offsets remaining that are needed in cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h which is intended as a temporary workaround only. In a later patch this file will be removed, too, and then auto-generated from the respective C structs. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com>
2009-06-12MPC512x: add more hardware description to immap_512x.hWolfgang Denk
- add GPIO module description - add Address Latch Timing Register description - add IO Control Memory Map - add FEC Memory Map Also change board/freescale/mpc5121ads/mpc5121ads.c and cpu/mpc512x/iopin.c as needed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com>
2009-06-1285xx: Fix MURAM size for MPC8569Haiying Wang
MPC8569 has 128K bytes MURAM. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-28Replace __attribute references with __attribute__Peter Tyser
__attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-04-05Update CHANGELOG, coding style cleanup.Wolfgang Denk
2009-04-04eSPI: add the eSPI register supportMingkai Hu
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
2009-04-04fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-04fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala
Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-0186xx: Cleanup MP supportKumar Gala
* Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx * Introduce determine_mp_bootpg() helper. We'll need this to address a bug introduced in v2009.03 with 86xx MP booting. We have to make sure to reserve the region of memory used for the MP bootpg() so other u-boot code doesn't use it. * Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to allow cmd_mp.c to build and work. In the future we should look at implementing all these functions. This could be common w/85xx if we use spin tables on 86xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30MPC85xx: Add MPC8569 CPU supportHaiying Wang
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30fsl-ddr: add the DDR3 SPD infrastructureDave Liu
- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
2009-03-30Add LSDMR (SDRAM Mode Register) definition on localbusKumar Gala
The masks for various bit defines of LSDMR are common and thus we can define them in one place rather than replicating them in each config.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-20Add LZO decompressor supportStefan Roese
This patch adds LZO decompression support to U-Boot. It is needed for the upcoming UBIFS support, since UBIFS uses LZO as default compressor/ decompressor. Since we only support read-only in UBIFS, only the decompressor is needed. All this is copied with minor changes from the current Linux kernel version (2.6.28-rc8). This patch only implements this LZO decompressor support for PPC. Other platforms using UBIFS will have to add the required "include/asm/unaligned.h" as well. It should be fairly easy to copy this from the Linux source tree as I have done it for PPC in this patch. Signed-off-by: Stefan Roese <sr@denx.de>
2009-03-20ppc: mark global bi_enet*addr as legacyMike Frysinger
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. In the ppc case, these things are part of the legacy ABI, so keep them around but mark them as legacy so no new code will touch them. Also stop calling load_sernum_ethaddr() since all boards now implement this as a stub. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com>
2009-03-09Add eTSEC 1/2 IO override control (corrected)ksi@koi8.net
This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.) Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
2009-02-23MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by defaultBecky Bruce
Currently, we get 256MB as the default, but since all the 86xx board configs define a 2G BAT mapping for RAM, raise default to 2G. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
2009-02-1683xx: Add eSDHC support on 8379 EMDS boardAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-1685xx: Add eSDHC support for 8536 DSAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-1632bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b10812
This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
2009-02-1686xx: Update CPU info output on bootupPeter Tyser
- Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-1686xx: Update Global Utilities structurePeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16mpc85xx: Add support for the P2020Srikanth Srinivasan
Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-1685xx: Fix how we map DDR memoryKumar Gala
Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-12ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham
The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
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