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Apply the same fix for 83xx as was done for 85xx in commit
96196a1f7546904563994d2d041804a816d7c139.
Without this, NAND SPLs are built with the text base intended for the main
image, resulting in a broken, very large u-boot-nand.bin.
The block of defines for NAND boot is moved closer to where
CONFIG_SYS_TEXT_BASE is defined. We can't directly use
CONFIG_SYS_NAND_U_BOOT_DST in the definition of CONFIG_SYS_TEXT_BASE because
autoconf.mk will include the literal text "CONFIG_SYS_NAND_U_BOOT_DST",
but at least keep them close and point out that they're supposed to be
the same.
Signed-off-by: Scott Wood <scottwood@freescale.com>
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CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
being able to use "sizeof(struct global_data)" in assembler files.
Recent experience has shown that manual synchronization is not
reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into
GENERATED_GBL_DATA_SIZE which gets automatically generated by the
asm-offsets tool. In the result, all definitions of this value can be
deleted from the board config files. We have to make sure that all
files that reference such data include the new <asm-offsets.h> file.
No other changes have been done yet, but it is obvious that similar
changes / simplifications can be done for other, related macro
definitions as well.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
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CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
some end address; to make the meaning more clear we rename it into
CONFIG_SYS_INIT_RAM_SIZE
No other code changes are performed in this patch, only minor editing
of white space (due to the changed length) and the comments was done,
where noticed.
Note that the code for the PATI and cmi_mpc5xx board configurations
looks seriously broken. Last known maintainers on Cc:
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
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Now that warm booting is not supported, there isn't a need for the
BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them.
Note that this change makes the board info bd_bootflags field useless.
It will always be set to 0, but we leave it around so that we don't
break the board info structure that some OSes are expecting to be passed
from U-Boot.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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Clean up Makefile, and drop a lot of the config.mk files on the way.
We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.
Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.
Signed-off-by: Wolfgang Denk <wd@denx.de>
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When planning for more generalization and Makefile cleanup it became
obvious that the introduction of a separate CONFIG_MK_ name space for
config options that were set through scripting in the Makefile was
not a good idea.
Originally the idea was to provide a script-free approach to supply
configuration options - there was no real need for a separate name
space. But when we now convert the existing Makefile entries to make
use of this approach, it would mean that we have to touch a large
number of board config files and add #ifdef / #define sequences to
"convert" from the CONFIG_MK_ to the CONFIG_ name space.
It seems much cleaner to get rid of this somewhat arbitrary _MK
string now for the few boards that actually use it.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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Newer Linux kernels can overrun the initial memory window used for
booting with their BSS area. When this happens, they overwrite the FDT
and silently fail to boot.
On e300 CPUs, the Linux kernel uses an initial BAT covering the first
256MB of RAM. See arch/powerpc/kernel/head_32.S for details. Increase
the value of CONFIG_SYS_BOOTMAPSZ to accommodate the maximum value
allowed by Linux. This will allow very large kernels to boot.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The default partition table matches the .dts files for these boards in
Linux. This allows these partitions to be used by name with U-Boot's
"nand" command.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch removes the completely unused CONFIG_SERIAL_SOFTWARE_FIFO
feature from U-Boot. It has only been implemented for PPC4xx and was not
used at all. So let's remove it and make the code smaller and cleaner.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
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Some parts that have an Enhanced Local Bus Controller weren't
setting CONFIG_FSL_ELBC. Fix this so we can use this define
properly going forward (currently it's only used if PHYS_64BIT is
set, which meant not all platforms needed to have it set correctly).
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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because it's convenient.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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and avoid e.g., two identical boards from causing random networking
conflicts when hooked up to the same network.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The core support for NAND booting is there already, so this patch
is pretty straightforward.
There is one trick though: top level Makefile expects nand_spl to
be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code
from mpc8313erdb boards, and so to not duplicate the code we just
symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
o silence make during ln echo
o update documentation
o and avoid:
$ ./MAKEALL MPC8315ERDB_NAND
Configuring for MPC8315ERDB board...
sdram.o: In function `fixed_sdram':
/home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay'
by renaming udelay -> __udelay in the spirit of commit
3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog
support".
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
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some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.
Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.
also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.
also start to use i/o accessors.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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linux mpc83xx_defconfig kernels are getting bigger, accommodate for
their growth by adjusting default load and fdt addresses.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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the former
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch simply converts the board to the hwconfig infrastructure.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
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When enabling NAND support for a board, one must also define
CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c
for correct output.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Ron Madrid <ron_madrid@sbcglobal.net>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
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This patch adds CONFIGs for enabling USB in mpc8315erdb and also
adds usb_phy_type in CONFIG_EXTRA_ENV_SETTINGS. Also revamps its
Copyright.
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
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Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The CONFIG_CMD_ENV option controls enablement of the `saveenv` command
rather than a generic "env" command, or anything else related to the
environment. So, let's make sure the define is named accordingly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Signed-off-by: Dave Liu <daveliu@freescale.com>
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MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's
support them.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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modify the CAS timings. my understanding is that these
settings decrease various wait times in the DDR interface.
Because these wait times are in clock cycles, and the DDR
clock on the 8315 RDB runs slower than on some other 83xx
platforms, we can dial down these values without a problem,
thereby decreasing the latency of memory a little.
Signed-off-by: Howard Gregory <Greg.Howard@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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the operating system may leave flash in a h/w locked state after writing.
This allows u-boot to continue to write flash by enabling h/w unlocking
by default.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI
support, or without TSEC1 but with USB ULPI PHY support in addition.
With this patch user can specify desired USB PHY.
Also, it seems that we can't distinguish the two boards in software, so
user have to set `mpc8315erdb' environment variable to either 'tsec1'
(TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that
Linux will not probe for TSEC1.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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move the BRx_* and ORx_* left behind in mpc85xx.h
The same is needed for mpc8xx.h and mpc8260.h (defines are almost
the same, just few differences which needs some attention though).
But the bad news for mpc8xx and mpc8260 is that there are a lot of users
of these defines. So this cleanup I'll leave for the "better times".
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Change all code that conditionally operates on high bat
registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
instead of the myriad ways this is done now. Define the option
for every config for which high bats are supported (and
enabled by early boot, on parts where they're not always
enabled)
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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this seems as a good compromise between human memory, typing,
and last but not least, to accommodate for current and future kernel bloat.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Dave Liu <daveliu@freescale.com>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.
Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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The features list:
- Boot from NOR Flash
- DDR2 266MHz hardcoded configuration
- Local bus NOR Flash R/W operation
- I2C, UART, MII and RTC
- eTSEC0/1 support
- PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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