summaryrefslogtreecommitdiff
path: root/include/configs/MPC8536DS.h
AgeCommit message (Collapse)Author
2009-02-1685xx: Add eSDHC support for 8536 DSAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Handle eLBC difference w/36-bit physicalKumar Gala
The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-2385xx: Use BR_ADDR macro for NAND chipselectsKumar Gala
Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-2385xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala
Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala
Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-2385xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: separate FLASH BASE virtual from physical addressKumar Gala
Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-2385xx: separate PIXIS virtual from physical addressKumar Gala
Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-12-14Remove unused CONFIG_ADDR_STREAMING definesPeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-03Removed unused CONFIG_L1_INIT_RAM symbol.Jon Loeliger
Prevent further viral propogation of the unused symbol CONFIG_L1_INIT_RAM by just removing it. Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-0385xx: remove the unused ddr_enable_ecc in the board fileDave Liu
The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2008-10-31NAND: Add NAND support for MPC8536DS boardJason Jin
This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file. It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image. Singed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-2485xx: Convert all fsl_pci_init users to new APIsKumar Gala
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-2485xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-2485xx: remove unused config definitionDave Liu
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-18Enabled the Freescale SGMII riser card on 8536DSJason Jin
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-1885xx: Enable interrupt and setexpr commands on Freescale 85xx boardsKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-07Remove redundant #define for MPC8536DSHaiying Wang
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-10-07Fix the incorrect DDR clk freq reporting on 8536DSJason Jin
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-09-10rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10cmd_mac: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD
finish remaning CFG_ID_EEPROM in CONFIG_ID_EEPROM start in commit ad8f8687b78c3e917b173f038926695383c55555 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-27mpc85xx: Add support for the MPC8536DS reference boardKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit (git 2.34.1) at 2024-12-27 06:43:17 +0000