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path: root/include/configs/coreboot.h
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2013-04-15x86: config: Init PCI before SPISimon Glass
Since the ICH SPI controller uses PCI, we must ensure that PCI is available before it is inited. This fixes the current "ICH SPI: Cannot find device" message on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-20Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini
2013-03-19x86: Enable time command for corebootSimon Glass
This command is useful for measuring SPI flash load times and the like. Enable gettime as well to obtain absolute time tick values. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19x86: Enable SPI flash support for corebootSimon Glass
Turn on SPI flash support and related commands. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-18x86: Enable USB features for corebootSimon Glass
Enable PCI EHCI, storage, keyboard and Ethernet for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04x86: Enable CONFIG_OF_CONTROL on corebootSimon Glass
Make use of a device tree on coreboot boards, and set the default to link. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-14x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTORSimon Glass
Invert the polarity of this option to simplify the Makefile logic. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Gabe Black <gabeblack@chromium.org>
2012-12-26x86: coreboot: Enable io commandSimon Glass
Enable the io command for x86 on coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Fix coreboot config to boot on ChromebookSimon Glass
The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Turn on support for EFI's GPT in the coreboot configGabe Black
This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: coreboot: Enable video displaySimon Glass
Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer
This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass
Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Enable ICH6 GPIO controller for corebootSimon Glass
Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass
This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Select stdio devices for corebootSimon Glass
We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: coreboot: Enable LPC TPMSimon Glass
Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Remove coreboot start16 codeSimon Glass
Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Put global data on the stackGraeme Russ
Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-02x86: config: Enable AHCI support for corebootSimon Glass
Enable AHCI driver for Intel SATA devices. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-22config: Enable CBFS, ext4 for corebootSimon Glass
Enable Coreboot and EXT4 Filesystems on the coreboot board. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-15serial: Remove CONFIG_SERIAL_MULTI from config filesMarek Vasut
Remove any notion of CONFIG_SERIAL_MULTI from board config files. Since CONFIG_SERIAL_MULTI is now enabled by default, it is useless to specify this config option in the board config files. Therefore remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
2012-02-12configs: Remove CONFIG_NET_MULTI from board filesFabio Estevam
CONFIG_NET_MULTI is not used anymore, so remove it from board files. Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kumar Gala <kumar.gala@freescale.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefano Babic <sbabic@denx.de> Tested-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Heiko Schocher <hs@denx.de>
2011-12-19x86: Initial commit for running as a coreboot payloadGabe Black
Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black <gabeblack@chromium.org>
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