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This patch adds support for the a3m071 board based on the
MPC5200.
Signed-off-by: Stefan Roese <sr@denx.de>
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This option protects the printf() functions from overflow.
Signed-off-by: Simon Glass <sjg@chromium.org>
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We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Coreboot boards have an LPC TPM connected, so enable this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
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board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :
#ifdef CONFIG_FSL_SATA_V2
...
#endif
To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.
This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the
boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced
CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed
converting a few boards over to the new option. Fix this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
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- Sort by address, and fix column alignment
- Don't label things as localbus that aren't. Instead, put chipselect
info at the end of the description for localbus windows. Note that
NAND/NOR have their chipselects swapped when booting from NAND, and CS2
can be either PMC or VSC7385 depending on hwconfig.
- Shrink NAND to the 32K that's actually mapped in the localbus
- Assign an address and size to L2 SRAM. Remove the similarly named
but unintelligible "L2 SDRAM(REV.)".
- Remove the untrue comment about L1 stack being mapped with TLB0.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
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Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
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Enable using of new MUSB framework on Beagle.
NOTE! This is not just a change of backend code: top-level behavior
is also changed, we now use USB device port for USB Ethernet instead
of serial.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
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Add initialization for new MUSB framework.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
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Use new musb framework instead of the old one on AM3517_EVM.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
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Enable musb gadget in Ethernet mode on port 0 and
musb host on port1.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
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Enable USB keyboard for seaboard and ventana
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
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Move environment settings for stdin/stdout/stderr to
tegra-common-post.h and generate them automaticaly based on input
device selection.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
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CONFIG_EHCI_DCACHE was removed by commit b8adb12
"USB: Drop cache flush bloat in EHCI-HCD". Remove the defines from
the boards configs as well.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
cc: Marek Vasut <marex@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Tom Rini <trini@ti.com>
cc: Wolfgang Denk <wd@denx.de>
cc: Thierry Reding <thierry.reding@avionic-design.de>
cc: Tom Warren <twarren@nvidia.com>
cc: Stephen Warren <swarren@nvidia.com>
cc: Stefano Babic <sbabic@denx.de>
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Modify tegra-common-post.h's BOOTCOMMAND definition to use the generic
filesystem command load rather than separate fatload and ext2load.
This removes the need to iterate over supported filesystem types in the
boot command.
This requires editing all board config headers to enable the new
commands. The now-unused commands are left enabled to assue backwards
compatibility with any user scripts. Boards (all from Avionic Design)
which define custom BOOTCOMMAND values are not affected.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
tegra generic fs cmds fixup
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The NAND defines ended up before this include file, but should be after
it, so it doesn't become a post-pre-NAND.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Now that we are using the new CONFIG_SYS_NAND_SELF_INIT setup, we don't
need CONFIG_SYS_NAND_BASE. Punt it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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TrimSlice's USB1 port has two purposes; it either acts as a device port
hosting Tegra's USB recovery protocol, or acts as a host port connected
to the internal USB->SATA bridge chip, which may in turn be connected to
an SSD or HDD. Add the appropriate device tree and board configuration
options to enable this port as a host port, and route the port to the
SATA bridge using the VBUS GPIO.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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Enable the Seaboard's 16-bit LCD and use it as the console.
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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For tegra we want to enable the cache for the LCD. This is easier if
we can avoid using L2 page tages, so align the LCD to a section
boundary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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These platforms don't include dcache support. Define CONFIG_SYS_DCACHE_OFF
so that functions don't try to call non-existent routines like
flush_dcache_range().
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matt Sealey <matt@genesi-usa.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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One second is enough time for users to react in case they want to stop the
booting process.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
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Use EHCI MXC configuration options for i.MX25.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matthias Weisser <weisserm@arcor.de>
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This patch enables SPI Booting for EXYNOS5
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch enables SPI driver for EXYNOS5.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch enables sound support for EXYNOS5
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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