Age | Commit message (Collapse) | Author | |
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2018-01-19 | ARC: HSDK: CGU: Update AXI, TUN, ARC clock options | Eugeniy Paltsev | |
Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> | |||
2017-12-11 | ARC: clk: introduce HSDK CGU clock driver | Eugeniy Paltsev | |
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> |