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path: root/include/mpc83xx.h
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2009-06-1283xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser
Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-1683xx: add missing TIMING_CFG1_CASLAT_* definesHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-02-1683xx: Add eSDHC support on 8379 EMDS boardAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-01-21mpc83xx: Add support for MPC83xx PCI-E controllersAnton Vorontsov
This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-2183xx: PCI agent mode fixes for multi-board systemsIra Snyder
When running a system with 2 or more MPC8349EMDS boards in PCI agent mode, the boards will lock up the PCI bus by scanning against each other. The boards lock against each other by trying to access the PCI bus before clearing their configuration lock bit. Both boards end up in a loop, sending and receiving "Target Not Ready" messages forever. When running in PCI agent mode, the scanning now takes place after the boards have cleared their configuration lock bit. Also, add a missing declaration to the mpc83xx.h header file, fixing a build warning. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-11-19powerpc: 83xx: add missing TIMING_CFG1_CASLAT_* definesHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-29Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-21mpc83xx: add TSECs' HRCWH masks for MPC837x processorsAnton Vorontsov
We'll use these masks to parse TSEC modes out of HRCWH. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-24mpc83xx: Fix typo in include/mpc83xx.hNobuhiro Iwamatsu
Fixed typo from CONIFG_MPC837X to CONFIG_MPC837X Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-25MPC83XX: Add miscellaneous registers and #defines to support MPC83xx family ↵Nick Spence
devices This patch adds elements to the 83xx sysconf structure and #define values that are used by mpc83xx family devices. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-08-12NAND boot: MPC8313ERDB supportScott Wood
Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-07-14fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips
Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-1083xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.hAnton Vorontsov
This patch moves Freescale Localbus defines out of mpc83xx.h, so we could use it on MPC85xx and MPC86xx processors. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-10Add missing CSCONFIG_BANK_BIT_3 define to mpc83xx.hTor Krill
Signed-off-by: Tor Krill <tor@excito.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) codeKim Phillips
in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6, 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing and processor ID display. Add REVID_{MAJ,MIN}OR macros to make REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR convenience macros. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25mpc83xx: MPC8360E-RDK: rework ddr setup, enable eccAnton Vorontsov
Current DDR setup easily causes memory corruption, this patch fixes it. Also fix TIMING_CFG0_MRS_CYC definition. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc8323erdb: Improve the system performanceMichael Barkowski
The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-17mpc83xx: Fix the fatal conflict of mergeDave Liu
The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 will cause the mpc8315erdb board can't boot up. The patch fix that bug, and remove the duplicated #ifdef CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for MPC8313E processor. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16mpc83xx: add support for more system clock performance controlsKim Phillips
System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-10mpc83xx: Fix the wrong definition of MPC8315EDave Liu
According to the latest user manual of MPC8315E, 1) The SVCOD of HRCWL is different than 837x 2) The SCCR has changes Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-10mpc83xx: Fix the typo in mpc83xx.hDave Liu
The SPCR about TSEC priority is wrong. Signed-off-by: Michael Barkowski <Michael.Barkowski@freescale.com> Signed-off-by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-08mpc83xx: Add the support of MPC8315E SoCDave Liu
The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-01-08mpc83xx: Add the support of MPC837x SoCDave Liu
The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-08-16mpc83xx: implement board_add_ram_infoKim Phillips
add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10Update SCCR programming in cpu_init_f() to support all 83xx processorsTimur Tabi
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-08-10mpc83xx: Add support for 8360 silicon revision 2.1Lee Nipper
This change adds 8360 silicon revision 2.1 support to u-boot. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-06-22Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk
2007-06-22[ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
2007-04-23mpc83xx: Add generic PCI setup code.Scott Wood
Board code can now request the generic setup code rather than having to copy-and-paste it for themselves. Boards should be converted to use this once they're tested with it. Signed-off-by: Scott Wood <scottwood@freescale.com>
2007-04-23mpc83xx: Add register definitions for MPC831x.Scott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com>
2007-03-02mpc83xx: Fix config of Arbiter, System Priority, and Clock ModeKumar Gala
The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDSXie Xiaobo
MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2007-03-02mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDSXie Xiaobo
MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
2007-03-02mpc83xx: Add support for the MPC8349E-mITX-GPTimur Tabi
Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: Timur Tabi <timur@freescale.com>
2007-03-02mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X insteadKumar Gala
The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02mpc83xx: Add support for the MPC832XEMDS boardDave Liu
This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02mpc83xx: streamline the 83xx immr head fileDave Liu
For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-11-03mpc83xx: Add MPC8360EMDS basic board supportDave Liu
Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
2006-11-03mpc83xx: Changed to unified mpx83xx names and added common 83xx changesDave Liu
Incorporated the common unified variable names and the changes in preparation for releasing mpc8360 patches. Signed-off-by: Dave Liu <daveliu@freescale.com>
2005-10-11Added support for TQM834x boards.Marian Balakowicz
2005-08-01Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger
- C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
2005-07-28* Patch by Eran LibertyEran Liberty
Add support for the Freescale MPC8349ADS board.
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