| Age | Commit message (Collapse) | Author |
|---|
|
This uses the new MMC framework
Some contributions by Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
Here's a new framework (based roughly off the linux one) for managing
MMC controllers. It handles all of the standard SD/MMC transactions,
leaving the host drivers to implement only what is necessary to
deal with their specific hardware.
This also hooks the infrastructure into the PowerPC board code
(similar to how the ethernet infrastructure now hooks in)
Some of this code was contributed by Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
The current MMC infrastructure relies on the existence of an
arch-specific header file. This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
This is to get it out of the way of incoming MMC framework
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
MMC cards are not memory, so we stop treating them that way.
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
This errata fix is required for 32 bit DDR2 controller on 8572.
May also be required for P10XX20XX platforms
Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
|
|
The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory,
CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module
with "$ make TQM8548_AG_config".
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
|
|
The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN
interface. With NAND support, the image is significantly larger and
TEXT_BASE is adjusted accordingly. U-Boot can be built for this
module with "$ make TQM8548_BE_config".
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
|
|
The TQM8548_AG module does not have the standard PCI/PCI-X interface
connected but just the PCI Express interface . So far it was not
possible to disable it without disabling the complete PCI interface
(CONFIG_PCI) including PCI Express.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
|
|
- Update style of 86xx CPU information on boot to more closely
match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output
== Before ==
Freescale PowerPC
CPU:
Core: E600 Core 0, Version: 0.2, (0x80040202)
System: Unknown, Version: 2.1, (0x80900121)
Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC
== After ==
CPU: 8641D, Version: 2.1, (0x80900121)
Core: E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
CPU:1066.667 MHz, MPX:533.333 MHz
DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1: D-cache 32 KB enabled
I-cache 32 KB enabled
L2: 512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
|
|
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
|
|
Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
|
|
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map. Additionally, the change to the address
map exposes a small issue in our dummy read on the ULI bus. We need
to use the new mapping functions to handle that read properly in the
36-bit config.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
|
|
The Blackfin i2c driver has been rewritten thus the special ifdefs in the
common code are no longer needed.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
|
|
With actual u-boot compiling the mgcoge port fails, because
since commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56 it is
necessary to define CONFIG_NET_MULTI.
Seems to me the mgcoge port is the only actual existing 8260
port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed
to be fixed.
Signed-off-by: Heiko Schocher <hs@denx.de>
|
|
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.
On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".
This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.
The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.
The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration. The default will be the
"T2 Sample" value. A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".
Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is
included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB.
It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx
boards right now.
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|
At some point an intentional double space at the end of the sentence
got changed into a tab in the GPL header line:
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
This patch fixes the damage.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
|
|
|
|
If on your board is more than one flash, you must know
the size of every single flash, for example, for updating
the DTS before booting Linux. So make this function
flash_get_info() extern, and you can have all info
about your flashes.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
Added new CONFIG options for the three type of MAC-PHY interconnect and
applied them all relevant board config files
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
|
|
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
between the two current users (lib_ppc/board.c, 44x SPD DDR2).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
|
|
We have common defines that we duplicate in various ways. Having an
arch specific config.h gives us a common location for those defines.
Eventually we should be able to replace this when we have proper
Kconfig support.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
Now that the rest of u-boot can support it, change the PCI bus
address of the PCI MEM regions from 0x80000000 to 0xc0000000,
and use the same bus address for both PCI1 and PCI2. This will
maximize the amount of PCI address space left over to map RAM
on systems with large amounts of memory.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
Clean up PCI mapping concepts in the 8641 config - rename _BASE
to _BUS, as it's actually a PCI bus address, separate virtual
and physical addresses into _VIRT and _PHYS, and use each
appopriately.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
If CONFIG_ADDR_MAP is enabled, update the address map
whenever we write a bat.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
The BAT fields are architected; there's no need for these to be in
cpu-specific files. Drop the duplication and move these to
include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only
used by the alaska board, and switch to using the BATU_BL_xxx defines
used by all the other boards. The BL_ defines previously in use
had to be shifted into the proper position for use, which was inefficient.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
It is no longer always true that the pci bus address can be
used as the virtual address for pci accesses. pci_map_bar()
is created to return the virtual address for a pci region.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
If the VA and PA of the flash aren't the same, the banks list
should be initialized to hold the physical address. Correct this.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
|
|
This patch adds support for Dave/DENX QongEVB-LITE i.MX31-based board.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
|
Driver for Dave DNET ethernet controller (used on Dave/DENX
QongEVB-LITE board).
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
|
|
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.
Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
Added definitions for i.MX31 processor GPIO registers.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
|
|
|
|
|
|
|
|
|
|
Enable NAND_UNLOCK option for unlocking nand for
erase/write operations
Signed-off-by: Nishanth Menon <nm@ti.com>
|
|
Add missing GPIO registers address definition for Coldfire M5271.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
|
|
Cleanup for M5271EVB:
Added clarification on the use of CONFIG_SYS_CLOCK.
Modified to use u-boot's HUSH parser.
Cleanup on environment settings.
Removed compiler warning by defining CONFIG_SYS_CS0_*
Dependencies:
Added the use of CONFIG_SYS_MCF_SYNCR for clock multiplier.
This depends on a patch to include/asm-m68k/m5271.h
that defines the multiplier and divider ratios.
Removed the definition of CONFIG_SYS_FECI2C.
This depends on a patch that removes the use of it in
cpu/mcf52x2/cpu_init.c
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
|
|
M5271 dynamic clock multiplier. It is currently fixed at 100MHz.
Allow the board header file to set their own multiplier and divider.
Added the #define for the multiplier and divider to the cpu header file.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
|
|
Move the default SPI CS that we boot from into common code so that it can
be used in other SPI drivers and environment settings.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
include/flash.h was commented to say that the address in
flash_info->start was a physical address. However, from u-boot's
point of view, and looking at most flash code, it makes more
sense for this to be a virtual address. So I corrected the
comment to indicate that this was a virtual address.
The only flash driver that was actually treating the address
as physical was the mtd/cfi_flash driver. However, this code
was using it inconsistently as it actually directly dereferenced
the "start" element, while it used map_physmem to get a
virtual address in other places. I changed this driver so
that the code which initializes the info->start field calls
map_physmem to get a virtual address, eliminating the need for
further map_physmem calls. The code is now consistent.
The *only* place a physical address should be used is when defining the
flash banks list that is used to initialize the flash_info struct,
usually found in the board config file.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Stefan Roese <sr@denx.de>
|
